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72V70800TFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
10
COMMERCIAL TEMPERATURE RANGE
IDT72V70800 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS
NOTE:
1. n denotes an input stream number from 0 to 3.
Name
(1)
Description
OFn2, OFn1, OFn0 These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to
(Offset Bits 2, 1 & 0) start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse
input signal is applied to the F0i input of the device. See Figure 5.
DLEn
(Data Latch Edge) ST-BUS
®
mode: DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.
GCI mode: DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.
Read/Write Address: 03
H
Reset Value: 0000H
1514131211109876543210
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR Register
11
IDT72V70800 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIAL TEMPERATURE RANGE
ST-BUS
®
F0i
RX Stream
5709 drw05
Bit 7
Bit 7
CLK
Bit 7
Bit 7
denotes the 3/4 point of the bit cell
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
GCI F0i
Bit 0
Bit 0
CLK
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
TABLE 9 — OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS
(FD11, FD2-0)
Figure 5. Examples for Input Offset Delay Timing
Measurement Result from Corresponding
Input Stream Frame Delay Bits Offset Bits
Offset
FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn
No clock period shift (Default) 1000000 0
+ 0.5 clock period shift 0000000 1
+ 1.0 clock period shift 1001001 0
+ 1.5 clock period shift 0001001 1
+ 2.0 clock period shift 1010010 0
+ 2.5 clock period shift 0010010 1
+ 3.0 clock period shift 1011011 0
+ 3.5 clock period shift 0011011 1
+ 4.0 clock period shift 1100100 0
+ 4.5 clock period shift 0100100 1
12
COMMERCIAL TEMPERATURE RANGE
IDT72V70800 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
TABLE 10 ” CONNECTION MEMORY BITS
NOTE:
1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel
and stream associated with this location.
Bit Name Description
15 LPBK When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback
(Per Channel Loopback) operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.
14 V/C This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a
(Variable/Constant per-channel basis.
Throughput Delay)
13 PC When 1, the contents of the connection memory are output on the corresponding output channel and stream.
(Processor Channel) Only the lower byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection
memory are the data memory address of the switched input channel and stream.
12 CCO This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.
(Control Channel Output)
11 OE This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions
(Output Enable) normally. When 0, the output driver is in a high-impedance state.
10-9 Unused Must be zero for normal operation.
8,7
(1)
SAB1-0 The binary value is the number of the data stream for the source of the connection.
(Source Stream Address Bits)
6-0
(1)
CAB6-0 The binary value is the number of the channel for the source of the connection.
(Source Channel Address Bits)
1514131211109876543210
LPBK V/C PC CCO OE 0 0 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

72V70800TFG

Mfr. #:
Buy 72V70800TFG
Manufacturer:
IDT
Description:
Digital Bus Switch ICs 3.3V 512X512 TIS SWITCH
Lifecycle:
New from this manufacturer.
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