Document Number: 38-05283 Rev. *P Page 13 of 25
Switching Characteristics
Over the Operating Range
Parameter
[13, 14]
Description
200 MHz 167 MHz
Unit
Min Max Min Max
t
POWER
V
DD
(Typical) to the First Access
[15]
1–1–ms
Clock
t
CYC
Clock Cycle Time 5.0 – 6.0 – ns
t
CH
Clock HIGH 2.0 – 2.4 – ns
t
CL
Clock LOW 2.0 – 2.4 – ns
Output Times
t
CO
Data Output Valid After CLK Rise – 3.0 – 3.4 ns
t
DOH
Data Output Hold After CLK Rise 1.3 – 1.5 – ns
t
CLZ
Clock to Low Z
[16, 17, 18]
1.3–1.5–ns
t
CHZ
Clock to High Z
[16, 17, 18]
– 3.0 – 3.4 ns
t
OEV
OE LOW to Output Valid – 3.0 – 3.4 ns
t
OELZ
OE LOW to Output Low Z
[16, 17, 18]
0–0–ns
t
OEHZ
OE HIGH to Output High Z
[16, 17, 18]
– 3.0 – 3.4 ns
Setup Times
t
AS
Address Setup Before CLK Rise 1.4 – 1.5 – ns
t
ADS
ADSC, ADSP Setup Before CLK Rise 1.4 – 1.5 – ns
t
ADVS
ADV Setup Before CLK Rise 1.4 – 1.5 – ns
t
WES
GW, BWE, BW
X
Setup Before CLK Rise 1.4 – 1.5 – ns
t
DS
Data Input Setup Before CLK Rise 1.4 – 1.5 – ns
t
CES
Chip Enable Setup Before CLK Rise 1.4 – 1.5 – ns
Hold Times
t
AH
Address Hold After CLK Rise 0.4 – 0.5 – ns
t
ADH
ADSP, ADSC Hold After CLK Rise 0.4 – 0.5 – ns
t
ADVH
ADV Hold After CLK Rise 0.4 – 0.5 – ns
t
WEH
GW, BWE, BW
X
Hold After CLK Rise 0.4 – 0.5 – ns
t
DH
Data Input Hold After CLK Rise 0.4 – 0.5 – ns
t
CEH
Chip Enable Hold After CLK Rise 0.4 – 0.5 – ns
Notes
13. Timing reference level is 1.5 V when V
DDQ
= 3.3 V and is 1.25 V when V
DDQ
= 2.5 V.
14. Test conditions shown in (a) of Figure 2 on page 12 unless otherwise noted.
15. This part has an internal voltage regulator; t
POWER
is the time that the power needs to be supplied above V
DD(minimum)
initially before a read or write operation can
be initiated.
16. t
CHZ
, t
CLZ
, t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of Figure 2 on page 12. Transition is measured ±200 mV from steady-state voltage.
17. At any possible voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
