CY7C1480V33
Document Number: 38-05283 Rev. *P Page 16 of 25
Figure 5. Read/Write Cycle Timing
[22, 23, 24]
Switching Waveforms (continued)
t
CYC
t
CL
CLK
ADSP
t
ADH
t
ADS
ADDRESS
t
CH
OE
ADSC
CE
t
AH
t
AS
A2
t
CEH
t
CES
BWE,
BW
X
D
ata Out (Q)
High-Z
ADV
Single WRITE
D(A3)
A4 A5 A6
D(A5) D(A6)
Data In (D)
BURST READBack-to-Back READs
High-Z
Q(A2)Q(A1)
Q(A4) Q(A4+1) Q(A4+2)
t
WEH
t
WES
Q(A4+3)
t
OEHZ
t
DH
t
DS
t
OELZ
t
CLZ
t
CO
Back-to-Back
WRITEs
A1
DON’T CARE UNDEFINED
A3
Notes
22. On this diagram, when CE
is LOW: CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH: CE
1
is HIGH, CE
2
is LOW, or CE
3
is HIGH.
23. The data bus (Q) remains in high Z following a write cycle, unless a new read access is initiated by
ADSP
or ADSC.
24. GW
is HIGH.
CY7C1480V33
Document Number: 38-05283 Rev. *P Page 17 of 25
Figure 6. ZZ Mode Timing
[25, 26]
Switching Waveforms (continued)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
A
LL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
25. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device.
26. DQs are in high Z when exiting ZZ sleep mode.
CY7C1480V33
Document Number: 38-05283 Rev. *P Page 18 of 25
Ordering Information
Ordering Code Definitions
Speed
(MHz) Ordering Code
Package
Diagram
Part and Package Type
Operating
Range
167 CY7C1480V33-167AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
200 CY7C1480V33-200AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
Temperature Range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Frequency Range: XXX = 167 MHz or 200 MHz
V
DD
= 3.3 V
Part Identifier: 1480 = SCD, 2 Mb × 36 (72 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAMs
Company ID: CY = Cypress
C 1480 V33 - CAXXXCY X7

CY7C1480V33-200AXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 72MB (2Mx36) 3.3v 200MHz Sync SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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