Description STM1404
10/36
Figure 6. Tamper pin (TP
1
or TP
3
) normally high (NH) external hookup (switch
open)
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
Figure 7. Tamper pin (TP
2
or TP
4
) normally low (NL) external hookup (switch
closed)
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
Figure 8. Tamper pin (TP
2
or TP
4
) normally low (NL) external hookup (switch open)
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
AI10461a
V
OUT
(STM1404A)
or
V
TPU
(STM1404B/C)
R
(1)
Switch Normally Open
Tamper Detection when Closed
TP
1
or TP
3
AI09699a
V
OUT
(STM1404A)
or
V
TPU
(STM1404B/C)
R
(1)
Switch Normally Closed;
Tamper Detection on Open
TP
2
or TP
4
AI10462a
V
OUT
(STM1404A)
or
V
TPU
(STM1404B/C)
R
(1)
Switch Normally Open;
Tamper Detection when Closed
TP
2
or TP
4
STM1404 Pin descriptions
11/36
2 Pin descriptions
See Figure 1: Logic diagram and Table 2: Signal names for a brief overview of the signals
connected to this device.
2.1 SAL, security alarm output (open drain)
This signal can be generated when ANY of the following conditions occur:
V
INT
> V
HV
, where V
HV
= upper voltage trip limit (4.2 V typ); and where V
INT
= V
CC
or
V
BAT
;
V
INT
< V
LV
, where V
LV
= lower voltage trip limit (2.0 V typ); and where V
INT
= V
CC
or
V
BAT
; or
When any of the physical tamper inputs, TP
1
to TP
4
, change from their normal states to
the opposite (i.e., intrusion of a physical enclosure).
T
A
> T
H
, where T
H
is an upper temperature trip limit specified by the customer (+80°C,
+85°C, and +95°C), factory-programmed (STM1404 only);
T
A
< T
L
, where T
L
is a lower temperature trip limit specified by the customer (–25°C or
–35°C), factory-programmed (STM1404 only);
Note: 1 The default state of the SAL
output during initial power-up is undetermined.
2 The alarm function will operate either with V
CC
on or when the part is internally switched
from V
CC
to V
BAT
.
2.2 TP
1
, TP
3
Physical tamper detect pin set normally to high (NH). They are connected externally through
a closed switch or a high-impedance resistor to V
OUT
(in the case of STM1404A) or V
TPU
(in
the case of STM1404B/C. A tamper condition will be detected when the input pin is pulled
low (see Figure 5 and Figure 6 on page 10). If not used, tie the pin to V
OUT
(for STM1404A)
or V
TPU
(for STM1404B/C).
2.3 TP
2
, TP
4
Physical tamper detect pin set normally to low (NL). They are connected externally through
a high-impedance resistor or a closed switch to V
SS
. A tamper condition will be detected
when the input pin is pulled high (see Figure 7 and Figure 8 on page 10). If not used, tie the
pin to V
SS
.
2.3.1 Vccsw, V
CC
switch output
This output is low when V
OUT
(see Section 2.10: V
OUT
on page 13) is internally switched to
V
CC
; in this mode it may be used to turn on an external p-channel MOSFET switch which
can source an external device directly from V
CC
for currents greater than 80 mA (bypassing
the STM1404).
This pin goes high when V
OUT
is internally switched to V
BAT
and may be used as a
“BATTERY ON” indicator.
Pin descriptions STM1404
12/36
If a security alarm (SAL) is issued on tamper, then the state of the Vccsw pin is as follows:
1. STM1404A (V
OUT
remains ON when SAL is active-low): Vccsw pin will continue to
operate in normal mode;
2. STM1404B (V
OUT
is taken to High-Z when SAL is active-low): Vccsw pin will be set to
high when this occurs; and
3. STM1404C (V
OUT
is driven to ground when SAL is active-low): Vccsw pin will be set to
high when this occurs.
2.4 BLD, V
BAT
low voltage detect output (open drain)
This is an internally loaded test of the battery, activated only during a power-up sequence to
insure that the battery is good either prior to or after encapsulation of the module. There are
three customer options for V
DET
:
2.3 V (2.5 V – external diode drop of about 0.2 V) for a 3 V lithium cell
2.5 V (2.7 V – 0.2 V) for a 3 V lithium cell or
3.2 V (3.4 V – 0.2 V) for a 3.68 V lithium “AA” battery
This output pin will go active-low when it detects a voltage on the V
BAT
pin below V
DET
. BLD
will be released when V
CC
drops below V
RST
.
2.5 Active-low RST output (open drain)
Goes low and stays low when V
CC
drops below V
RST
(Reset Threshold selected by the
customer), or when MR
is logic low. It remains low for t
rec
(200ms, typical) AFTER V
CC
rises
above V
RST
and MR goes from low to high.
2.6 MR, manual reset input
A logic low on MR asserts the RST output. The RST output remains asserted as long as MR
is low and for t
rec
after MR returns to high. This active low input has an internal 40 kΩ
(typical) pull-up resistor. It can be driven from a TTL or CMOS logic line or shorted to ground
with a switch. Leave it open if unused.
2.7 PFO, power-fail output (open drain)
When PFI is less than V
PFI
(power-fail input threshold voltage) or V
CC
falls below V
SW
(battery switchover threshold ~ 2.4 V), PFO
goes low, otherwise, PFO remains high. Leave
this pin open if unused.
2.8 PFI, power-fail input
When PFI is less than V
PFI
, or when V
CC
falls below V
SW
(see PFO, above), PFO goes
active-low. If this function is unused, connect this pin to V
SS
.

STM1404ATOHQ6F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Supervisory Circuits 3V FIPS 140 Security supervisor
Lifecycle:
New from this manufacturer.
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