Operation STM1404
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3 Operation
3.1 Reset input
The STM1404 security supervisor asserts a reset signal to the MCU whenever V
CC
goes
below the reset threshold (V
RST
), or when the push-button reset input (MR) is taken low.
RST
is guaranteed to be a logic low for 0 V < V
CC
< V
RST
if V
BAT
is greater than 1 V. Without
a backup battery, RST
is guaranteed valid down to V
CC
=1V.
During power-up, once V
CC
exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, t
rec
. After this interval RST returns high.
If V
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period (t
rec
). Any time V
CC
goes below the reset threshold
the internal timer clears. The reset timer starts when V
CC
returns above the reset threshold.
3.2 Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
rec
(see
Figure 25 on page 24) after it returns high. The MR
input has an internal 40 kΩ pull-up
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open-drain/collector outputs. Connect a normally open momentary switch from
MR
to ground to create a manual reset function; external debounce circuitry is not required.
If MR
is driven from long cables or the device is used in a noisy environment, connect a
0.1µF capacitor from MR
to V
SS
to provide additional noise immunity. MR may float, or be
tied to V
CC
when not used.
3.3 Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through V
OUT
. With a backup battery installed with voltage V
BAT
, the devices
automatically switch the SRAM to the backup supply when V
CC
falls.
Note: If backup battery is not used, connect both V
BAT
and V
OUT
to V
CC
.
This family of security supervisors does not always connect V
BAT
to V
OUT
when V
BAT
is
greater than V
CC
. V
BAT
connects to V
OUT
(through a 100Ω switch) when V
CC
is below V
SW
(~2.4 V) or V
BAT
(whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V
battery) to have a higher voltage than V
CC
.
Assuming that V
BAT
> 2.0 V, switchover at V
SO
ensures that battery backup mode is entered
before V
OUT
gets too close to the 2.0 V minimum required to reliably retain data in most
external SRAMs. When V
CC
recovers, hysteresis is used to avoid oscillation around the V
SO
point. V
OUT
is connected to V
CC
through a 3 Ω PMOS power switch.
Note: The backup battery may be removed while V
CC
is valid, assuming V
BAT
is adequately
decoupled (0.1 µF typ), without danger of triggering a reset.
