PCA9654E, PCA9654EA
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12
Register 3 − Configuration Register
This register configures the directions of the I/O pins. If
a bit in this register is set, the corresponding port pin is
enabled as an input with high−impedance output driver. If a
bit in this register is cleared, the corresponding port pin is
enabled as an output. At reset, the I/Os are configured as
inputs with a weak pull−up to V
DD
.
Table 12. CONFIGURATION REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol C7 C6 C5 C4 C3 C2 C1 C0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Power−on Reset
When power is applied to V
DD
, an internal Power−On
Reset (POR) holds the PCA9654E/PCA9654EA in a reset
condition until V
DD
has reached V
POR
. At that point, the
reset condition is released and the PCA9654E/ PCA9654EA
registers and state machine will initialize to their default
states. Thereafter, V
DD
must be lowered below 0.2 V to reset
the device.
For a power reset cycle, V
DD
must be lowered below
0.2 V and then restored to the operating voltage.
Interrupt Output
The open−drain interrupt output is activated when one of
the port pins changes state and the pin is configured as an
input. The interrupt is deactivated when the input returns to
its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may
cause a false interrupt to occur if the state of the pin does not
match the contents of the Input Port register.
I/O Port (Figure 2)
When an I/O is configured as an input, FETs Q1 and Q2
are off, creating a high−impedance input with a weak
pull−up (100 kW typ.) to V
DD
. The input voltage may be
raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2
is enabled, depending on the state of the Output Port register.
Care should be exercised if an external voltage is applied to
an I/O configured as an output because of the
low−impedance paths that exist between the pin and either
V
DD
or V
SS
.
