PCA9654E, PCA9654EA
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4
Table 2. MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD
DC Supply Voltage −0.5 to +7.0 V
V
I/O
Input / Output Pin Voltage −0.5 to +7.0 V
I
I
Input Current $20 mA
I
O
Output Current $50 mA
I
DD
DC Supply Current $100 mA
I
GND
DC Ground Current $200 mA
P
TOT
Total Power Dissipation 400 mW
P
OUT
Power Dissipation per Output 100 mW
T
STG
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction Temperature Under Bias 150 °C
q
JA
Thermal Resistance SOIC−16 (Note 1)
TSSOP−16
WQFN16
3 x 3 QFN16
4 x 4 QFN16
82
124
79
80
80
°C/W
P
D
Power Dissipation in Still Air at 85°C 190 mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 4000
> 400
N/A
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125°C (Note 5) $300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA / JESD78.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
DD
Positive DC Supply Voltage 1.65 5.5 V
V
I/O
Switch Input / Output Voltage 0 5.5 V
T
A
Operating Free−Air Temperature −55 +125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
PCA9654E, PCA9654EA
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Table 4. DC ELECTRICAL CHARACTERISTICS V
DD
= 1.65 V to 5.5 V, unless otherwise specified.
Symbol
Parameter Conditions
T
A
= −555C to +1255C
Unit
Min Typ Max
SUPPLIES
I
DD
Supply Current Operating mode; no load;
V
I
= V
DD
or 0 V; f
SCL
= 1 MHz
V
I
= V
DD
or 0 V; f
SCL
= 100 kHz
250
104
500
175
mA
I
STB
Standby Current Standby mode; no load;
V
I
= 0 V; f
SCL
= 0 Hz; I/O = inputs
V
I
= V
DD
; f
SCL
= 0 Hz; I/O = inputs
550
0.25
700
1
mA
V
POR
Power−On Reset Voltage (Note 6) 1.5 V
INPUT SCL; Input / Output SDA
V
IH
High−Level Input Voltage 0.7 x V
DD
V
V
IL
Low−Level Input Voltage 0.3 x V
DD
V
I
OL
Low−Level Output Current
V
OL
= 0.4 V; V
DD
< 2.3 V 10
mA
V
OL
= 0.4 V; V
DD
w 2.3 V 20
I
L
Leakage Current V
I
= V
DD
or GND $1
mA
C
I
Input Capacitance V
I
= GND 6 pF
I/Os
V
IH
High−Level Input Voltage 2.3 V V
CC
5.5 V
1.65 V V
CC
2.3 V
2.0
0.7 x V
DD
V
V
IL
Low−Level Input Voltage 2.3 V V
CC
5.5 V
1.65 V V
CC
2.3 V
0.8
0.3 x V
DD
V
I
OL
Low−Level Output Current
(Note 7)
V
OL
= 0.5 V; V
DD
= 1.65 V
V
OL
= 0.5 V; V
DD
= 2.3 V
V
OL
= 0.5 V; V
DD
= 3.0 V
V
OL
= 0.5 V; V
DD
= 4.5 V
8
12
17
25
13
22
28
37
mA
I
OL(tot)
Total Low−Level Output Current
(Note 7)
V
OL
= 0.5 V; V
DD
= 4.5 V 200 mA
V
OH
High−Level Output Voltage I
OH
= −3 mA; V
DD
= 1.65 V
I
OH
= −4 mA; V
DD
= 1.65 V
I
OH
= −8 mA; V
DD
= 2.3 V
I
OH
= −10 mA; V
DD
= 2.3 V
I
OH
= −8 mA; V
DD
= 3.0 V
I
OH
= −10 mA; V
DD
= 3.0 V
I
OH
= −8 mA; V
DD
= 4.5 V
I
OH
= −10 mA; V
DD
= 4.5 V
1.2
1.1
1.8
1.7
2.6
2.5
4.1
4.0
V
I
LH
Input Leakage Current V
DD
= 5.5 V; V
I
= V
DD
1
mA
I
LL
Input Leakage Current V
DD
= 5.5 V; V
I
= GND −100
mA
C
I/O
Input / Output Capacitance
(Note 8)
3.7 5 pF
INTERRUPT (INT)
I
OL
Low−Level Output Current V
OL
= 0.4 V 6 mA
C
O
Output Capacitance 2.1 5 pF
INPUTS AD0, AD1, AD2
V
IH
High−Level Input Voltage 2.3 V V
CC
5.5 V
1.65 V V
CC
2.3 V
2.0
0.7 x V
DD
V
V
IL
Low−Level Input Voltage 2.3 V V
CC
5.5 V
1.65 V V
CC
2.3 V
0.8
0.3 x V
DD
V
I
L
Leakage Current V
I
= V
DD
or GND $1
mA
C
I
Input Capacitance 2.4 5 pF
6. The power−on reset circuit resets the I
2
C bus logic with V
DD
< V
POR
and set all I/Os to logic 1 upon power−up. Thereafter, V
DD
must be lower
than 0.2 V to reset the part.
7. Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal bussing limits.
8. The value is not tested, but verified on sampling basis.
PCA9654E, PCA9654EA
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6
Table 5. AC ELECTRICAL CHARACTERISTICS V
DD
= 1.65 V to 5.5 V; T
A
= −55°C to +125°C, unless otherwise specified.
Symbol
Parameter
Standard
Mode
Fast Mode Fast Mode +
Unit
Min Max Min Max Min Max
f
SCL
SCL Clock Frequency 0 0.1 0 0.4 0 1.0 MHz
t
BUF
Bus−Free Time between a STOP and START
Condition
4.7 1.3 0.5
ms
t
HD:STA
Hold Time (Repeated) START Condition 4.0 0.6 0.26
ms
t
SU:STA
Setup Time for a Repeated START Condition 4.7 0.6 0.26
ms
t
SU:STO
Setup Time for STOP Condition 4.0 0.6 0.26
ms
t
HD:DAT
Data Hold Time 0 0 0 ns
t
VD:ACK
Data Valid Acknowledge Time (Note 9) 0.3 3.45 0.1 0.9 0.05 0.45
ms
t
VD:DAT
Data Valid Time (Note 10) 300 50 50 450 ns
t
SU:DAT
Data Setup Time 250 100 50 ns
t
LOW
LOW Period of SCL 4.7 1.3 0.5
ms
t
HIGH
HIGH Period of SCL 4.0 0.6 0.26
ms
t
f
Fall Time of SDA and SCL (Notes 12 and 13) 300 20 + 0.1C
b
(Note 11)
300 120 ns
t
r
Rise Time of SDA and SCL 1000 20 + 0.1C
b
(Note 11)
300 120 ns
t
SP
Pulse Width of Spikes Suppressed by Input Filter
(Note 14)
50 50 50 ns
PORT TIMING: C
L
v 100 pF (See Figures 7 and 10)
t
V(Q)
Data Output Valid Time 350 350 350 ns
t
SU(D)
Data Input Setup Time 100 100 100 ns
t
H(D)
Data Input Hold Time 1 1 1
ms
INTERRUPT TIMING: C
L
v 100 pF (See Figure 10)
t
V(INT_N)
Data Valid Time 4 4 4
ms
t
RST(INT_N)
Reset Delay Time 4 4 4
ms
9. t
VD:ACK
= time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
10.t
VD:DAT
= minimum time for SDA data out to be valid following SCL LOW.
11. C
b
= total capacitance of one bus line in pF.
12.A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to V
IL
of the SCL signal) in order to bridge
the undefined region SCL’s falling edge.
13.The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at 250 ns.
This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified t
f
.
14.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

PCA9654EDTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Interface - I/O Expanders 8-BIT I/O EXPANDER FOR I2
Lifecycle:
New from this manufacturer.
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