PCA9654E, PCA9654EA
www.onsemi.com
15
Characteristics of the I
2
C−Bus
The I
2
C−bus is for 2−way, 2−line communication between
different ICs or modules. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull−up resistor when
connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Figure 11).
Figure 11. Bit Transfer
data line
stable;
data valid
change
of data
allowed
SDA
SCL
START and STOP Conditions
Both data and clock lines remain HIGH when the bus is
not busy. A HIGH−to−LOW transition of the data line while
the clock is HIGH is defined as the START condition (S). A
LOW−to−HIGH transition of the data line while the clock is
HIGH is defined as the STOP condition (P) (see Figure 12).
Figure 12. Definition of START and STOP Conditions
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
System Configuration
A device generating a message is a ‘transmitter’; a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled
by the master are the ‘slaves’ (see Figure 13).
Figure 13. System Configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I
2
C−BUS
MULTIPLEXER
SLAVE
