PCA9654E, PCA9654EA
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16
Acknowledge
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge
related clock pulse; set−up time and hold time must be taken
into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
Figure 14. Acknowledgement of the I
2
C Bus
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
TIMING AND TEST SETUP
Figure 15. Definition of Timing on the I
2
C Bus
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
