PCA9654E, PCA9654EA
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7
Device Address
Following a START condition, the bus master must send
the address of the slave it is accessing and the operation it
wants to perform (read or write). The address of the
PCA9654E/PCA9654EA is shown in Figure 5. Slave
address pins AD2, AD1, and AD0 choose 1 of 64 slave
addresses. To conserve power, no internal pull−up resistors
are incorporated on AD2, AD1, and AD0. Address values
can be found on Table 6 “PCA9654E Address Map” and
Table 7 “PCA9654EA Address Map”.
Figure 5. PCA9654E / PCA9654EA Device Address
R/WA6 A5 A4 A3 A2 A1 A0
programmable
slave address
A logic 1 on the last bit of the first byte selects a read operation while a logic 0 selects a write operation.
Table 6. PCA9654E ADDRESS MAP
Address Input Slave Address
AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 HEX
GND SCL GND 0 0 1 0 0 0 0 20h
GND SCL VDD 0 0 1 0 0 0 1 22h
GND SDA GND 0 0 1 0 0 1 0 24h
GND SDA VDD 0 0 1 0 0 1 1 26h
VDD SCL GND 0 0 1 0 1 0 0 28h
VDD SCL VDD 0 0 1 0 1 0 1 2Ah
VDD SDA GND 0 0 1 0 1 1 0 2Ch
VDD SDA VDD 0 0 1 0 1 1 1 2Eh
GND SCL SCL 0 0 1 1 0 0 0 30h
GND SCL SDA 0 0 1 1 0 0 1 32h
GND SDA SCL 0 0 1 1 0 1 0 34h
GND SDA SDA 0 0 1 1 0 1 1 36h
VDD SCL SCL 0 0 1 1 1 0 0 38h
VDD SCL SDA 0 0 1 1 1 0 1 3Ah
VDD SDA SCL 0 0 1 1 1 1 0 3Ch
VDD SDA SDA 0 0 1 1 1 1 1 3Eh
GND GND GND 0 1 0 0 0 0 0 40h
GND GND VDD 0 1 0 0 0 0 1 42h
GND VDD GND 0 1 0 0 0 1 0 44h
GND VDD VDD 0 1 0 0 0 1 1 46h
VDD GND GND 0 1 0 0 1 0 0 48h
VDD GND VDD 0 1 0 0 1 0 1 4Ah
VDD VDD GND 0 1 0 0 1 1 0 4Ch
VDD VDD VDD 0 1 0 0 1 1 1 4Eh
GND GND SCL 0 1 0 1 0 0 0 50h
GND GND SDA 0 1 0 1 0 0 1 52h
GND VDD SCL 0 1 0 1 0 1 0 54h
GND VDD SDA 0 1 0 1 0 1 1 56h
VDD GND SCL 0 1 0 1 1 0 0 58h
VDD GND SDA 0 1 0 1 1 0 1 5Ah
VDD VDD SCL 0 1 0 1 1 1 0 5Ch
