NCP81274
www.onsemi.com
12
PWM_VID Interface
PWM_VID is a single wire dynamic voltage control
interface where the regulated voltage is set by the duty cycle
of the PWM signal applied to the controller.
The device controller converts the variable amplitude
PWM signal into a constant 2 V amplitude PWM signal
while preserving the duty cycle information of the input
signal. In addition, if the PWM_VID input is left floating,
the VID_BUFF output is tri-stated (floating).
The constant amplitude PWM signal is then connected to
the REFIN pin through a scaling and filtering network (see
Figure 6). This network allows the user to set the minimum
and maximum REFIN voltages corresponding to 0% and
100% duty cycle values.
Figure 6. PWM_VID Interface
PWM_VID
VID_BUFF
Internal
precision
reference
V
REF
= 2 V
GND
VREF
REFIN
R1
R2
R3
C1
0.1 mF
10n
Controller
The minimum (0% duty cycle), maximum (100% duty
cycle) and boot (PWM_VID input floating) voltages can be
calculated with the following formulas:
V
MAX
+ V
REF
@
1
1 )
R
1
@R
3
R
2
@
ǒ
R
1
)R
3
Ǔ
(eq. 1)
V
MIN
+ V
REF
@
1
1 )
R
1
@
ǒ
R
2
)R
3
Ǔ
R
2
@R
3
(eq. 2)
V
BOOT
+ V
REF
@
1
1 )
R
1
R
2
(eq. 3)
Soft Start
Soft start is defined as the transition from Enable assertion
high to the assertion of Power good as shown in Figure 4.
The output is set to the desired voltage in two steps, a fixed
initialization step of 1.5 ms followed by a ramp-up step
where the output voltage is ramped to the final value set by
the PWM_VID interface. During the soft start phase,
PGOOD pin is initially set low and will be set high when the
output voltage is within regulation and the soft start ramp is
complete. The PGOOD signal only de-asserts (pull low)
when the controller shuts down due to a fault condition
(UVLO, OVP or OCP event).
The output voltage ramp-up time is user settable by
connecting a resistor between pin PWM8/SS and GND. The
controller will measure the resistance value at power-up by
sourcing a 10 mA current through this resistor and set the
ramp time (t
ramp
) as shown in Table 16.
Remote Voltage Sense
A high performance true differential amplifier allows the
controller to measure the output voltage directly at the load
using the VSP (VOUT) and VSN (GND) pins. This keeps
the ground potential differences between the local controller
ground and the load ground reference point from affecting
regulation of the load. The output voltage of the differential
amplifier is set by the following equation:
V
DIFOUT
+
ǒ
V
VSP
* V
VSN
Ǔ
)
ǒ
1.3 V * V
REFIN
Ǔ
)
(eq. 4)
)
ǒ
V
DROOP
) V
CSREF
Ǔ
Where:
V
DIFOUT
is the output voltage of the differential amplifier.
V
VSP
− V
VSN
is the regulated output voltage sensed at the
load.
V
REFIN
is the voltage at the output pin set by the
PWM_VID interface.
V
DROOP
− V
CSREF
is the expected drop in the regulated
voltage as a function of the load current (load-line).
1.3 V is an internal reference voltage used to bias the
amplifier inputs to allow both positive and negative
output voltage for V
DIFOUT
.
Error Amplifier
A high performance wide bandwidth error amplifier is
provided for fast response to transient load events. Its
inverting input is biased internally with the same 1.3 V
reference voltage as the one used by the differential sense
amplifier to ensure that both positive and negative error
voltages are correctly handled.
An external compensation circuit should be used (usually
type III) to ensure that the control loop is stable and has
adequate response.
Ramp Feed-Forward Circuit
The ramp generator circuit provides the ramp used to
generate the PWM signals using internal comparators (see
Figure 7) The ramp generator provides voltage
feed-forward control by varying the ramp magnitude with
respect to the VRMP pin voltage. The PWM ramp time is
changed according to the following equation:
V
RAMPpk+pk
pp
+ 0.1 @ V
VRMP
(eq. 5)
The VRMP pin also has a UVLO function. The VRMP
UVLO is only active after the controller is enabled. The
VRMP pin is high impedance input when the controller is
disabled.
