NCP81274
www.onsemi.com
17
Table 9. PER PHASE OCP SETTINGS
Resistance
(kW)
Per Phase Voltage
(mV)
Latch Off Delay
(ms)
10 65 4
14.7 75 4
20 100 4
26.1 134 4
33.2 65 6
41.2 75 6
49.9 100 6
60.4 134 6
71.5 65 8
84.5 75 8
100 100 8
118.3 134 8
136.6 65 10
157.7 75 10
182.1 100 10
249 134 10
NOTE: 1% tolerance.
Under Voltage Lock-Out (VCC UVLO)
VCC is constantly monitored for the under voltage
lockout (UVLO) During power up both the VRMP and the
VCC pin are monitored Only after both pins exceed their
individual UVLO threshold will the full circuit be activated
and ready for the soft start ramp.
Over Voltage Protection
An output voltage monitor is incorporated into the
controller. During normal operation, if the output voltage is
400 mV over the REFIN value, the PGOOD pin will go low,
the DRON will assert low and the PWM outputs are set low.
The limit will be clamped at 2 V if REFIN is driven above
2 V. The outputs will remain disabled until the power is
cycled or the EN pin is toggled.
I
2
C Interface
The controller is connected to this bus as a slave device,
under the control of a master controller.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high
transition when the clock is high might be interpreted as
a stop signal. The number of data bytes that can be
transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave
devices can handle.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing
a START condition, defined as a high-to-low
transition on the serial data line SDA while the serial
clock line, SCL, remains high. This indicates that an
address/data stream will follow. All slave
peripherals connected to the serial bus respond to the
START condition, and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus an R/W
bit, which determines the direction of the data
transfer, i.e., whether data will be written to or read
from the slave device. The peripheral whose address
corresponds to the transmitted address responds by
pulling the data line low during the low period before
the ninth clock pulse, known as the Acknowledge
Bit. All other devices on the bus now remain idle
while the selected device waits for data to be read
from or written to it. If the R/W bit is a 0, the master
will write to the slave device. If the R/W bit is a 1, the
master will read from the slave device.
2. Data is sent over the serial bus in sequences of nine
clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device. Transitions
on the data line must occur during the low period of
the clock signal and remain stable during the high
period, as a low-to-high transition when the clock is
high may be interpreted as a STOP signal. The
number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is
limited only by what the master and slave devices
can handle.
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the
master will pull the data line high during the 10
th
clock pulse to assert a STOP condition. In READ
mode, the master device will override the
acknowledge bit by pulling the data line high during
the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then
take the data line low during the low period before
the tenth clock pulse, then high during the tenth
clock pulse to assert a STOP condition.
4. Any number of bytes of data may be transferred over
the serial bus in one operation, but it is not possible
to mix read and write in one operation because the
type of operation is determined at the beginning and
cannot subsequently be changed without starting
a new operation. To write data to one of the device
data registers or read data from it, the Address
Pointer Register must be set so that the correct data
register is addressed, and then data can be written
into that register or read from it. The first byte of
a write operation always contains an address that is
stored in the Address Pointer Register. If data is to be
written to the device, the write operation contains
a second data byte that is written to the register
selected by the address pointer register. The device
address is sent over the bus followed by R/W set to
0. This is followed by two data bytes. The first data
byte is the address of the internal data register to be
written to, which is stored in the Address Pointer
Register. The second data byte is the data to be
written to the internal data register.
