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NCP81274MNTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
NCP81274
www.onsemi.com
7
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(Unless otherwise stated: −10°C < T
A
< 100°C; 4.6 V < VCC < 5.4 V; C
VCC
= 0.1 mF)
Parameter UnitMaxTypMinSymbolTest Conditions
PGOOD
Output Low Voltage
I
PGOOD
= 10 mA (Sink) V
OL
0.4 V
Leakage Current P
GOOD
= 5 V I
L
0.2
mA
Output Voltage Initialization Time T_init 1.5 ms
Minimum Output Voltage Ramp
Time
T_ramp
MIN
0.15 ms
Maximum Output Voltage Ramp
Time
T_ramp
MAX
10 ms
PROTECTION-OCP, OVP, UVP
Under Voltage Protection (UVP)
Threshold
Relative to REFIN Voltage UVP 300 mV
Under Voltage Protection (UVP)
Delay
T
UVP
5
ms
Over Voltage Protection (OVP)
Threshold
Relative to REFIN Voltage OVP 400 mV
Over Voltage Protection (OVP)
Delay
T
OVP
5
ms
PWM OUTPUTS
Output High Voltage
Sourcing 500 mA
V
OH
VCC − 0.2 V
Output Mid Voltage V
MID
1.9 2.0 2.1 V
Output Low Voltage
Sinking 500 mA
V
OL
0.7 V
Rise and Fall Time
C
L
(PCB) = 50 pF, DV
O
= 10% to
90% of VCC
t
R
, t
F
10 ns
Tri-state Output Leakage G
x
= 2.0 V, x = 1−8, EN = Low I
L
−1.0 1.0
mA
Minimum On Time FSW = 600 kHz Ton 12 ns
0% Duty Cycle Comp Voltage when PWM Outputs
Remain LOW
VCOMP
0%
1.3 V
100% Duty Cycle Comp Voltage when PWM Outputs
Remain HIGH
VCOMP
100%
2.5 V
PWM Phase Angle Error Between Adjacent Phases ø ±15 °
PHASE DETECTION
Phase Detection Threshold
Voltage
CSP2 to CSP8 V
PHDET
VCC − 0.1 V
Phase Detect Timer CSP2 to CSP8 T
PHDET
1.1 ms
ERROR AMPLIFIER
Input Bias Current
I
BIAS
−400 400 nA
Open Loop DC Gain C
L
= 20 pF to GND,
R
L
= 10 kW to GND
G
OL
80 dB
Open Loop Unity Gain Bandwidth C
L
= 20 pF to GND,
R
L
= 10 kW to GND
GBW 20 MHz
Slew Rate
DV
IN
= 100 mV, G = −10 V/V,
DV
OUT
= 0.75–1.52 V, C
L
= 20 pF
to GND, R
L
= 10 kW to GND
SR 5
V/ms
Maximum Output Voltage I
SOURCE
= 2 mA V
OUT
3.5 V
Minimum Output Voltage I
SINK
= 2 mA V
OUT
1 V
NCP81274
www.onsemi.com
8
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(Unless otherwise stated: −10°C < T
A
< 100°C; 4.6 V < VCC < 5.4 V; C
VCC
= 0.1 mF)
Parameter UnitMaxTypMinSymbolTest Conditions
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
I
BIAS
−400 400 nA
VSP Input Voltage V
IN
0 2 V
VSN Input Voltage V
IN
−0.3 0.3 V
−3dB Bandwidth C
L
= 20 pF to GND,
R
L
= 10 kW to GND
BW 12 MHz
Closed Loop DC Gain
(VSP−VSN to DIFF)
VSP to VSN = 0.5 to 1.3 V G 1 V/V
Droop accuracy CSREF − DROOP = 80 mV,
V
REFIN
= 0.8 V to 1.2 V
DDROOP
78 82 mV
Maximum Output Voltage I
SOURCE
= 2 mA V
OUT
3 V
Minimum Output Voltage I
SINK
= 2 mA V
OUT
0.8 V
CURRENT SUMMING AMPLIFIER
Offset Voltage
V
OS
−500 500
mV
Input Bias Current CSSUM = CSREF = 1 V I
L
−7.5 7.5
mA
Open Loop Gain G 80 dB
Current sense Unity Gain
Bandwidth
C
L
= 20 pF to GND,
R
L
= 10 kW to GND
GBW 10 MHz
Maximum CSCOMP Output
Voltage
I
SOURCE
= 2 mA V
OUT
3.5 V
Minimum CSCOMP Output Voltage I
SINK
= 2 mA V
OUT
0.1 V
CURRENT BALANCE AMPLIFIER
Input Bias Current
CSP
X
− CSP
X+1
= 1.2 V I
BIAS
−50 50 nA
Common Mode Input Voltage
Range
CSP
X
= CSREF V
CM
0 2 V
Differential Mode Input Voltage
Range
CSREF = 1.2 V V
DIFF
−100 100 mV
Closed Loop Input Offset Voltage
Matching
CSP
X
= 1.2 V, Measured from the
Average
−1.5 1.5 mV
Current Sense Amplifier Gain 0 V < CSP
X
< 0.1 V G 5.7 6.0 V/V
Multiphase Current Sense Gain
Matching
CSREF = CSP = 10 mV to 30 mV
DG
−3 3 %
−3dB Bandwidth BW 8 MHz
IOUT
Input Reference Offset Voltage
ILIM to CSREF V
OS
−3 +3 mV
Output Current Max
ILIM Sink Current 20 mA
I
OUT
200
mA
Current Gain
IOUT/ILIM, R
LIM
= 20 kW,
R
IOUT
= 5 kW
G 9.5 10 10.5 A/A
VOLTAGE REFERENCE
VREF Reference Voltage
I
REF
= 1 mA VREF 1.98 2 2.02 V
VREF Reference accuracy T
JMIN
< T
J
< T
JMAX
DVREF
1 %
NCP81274
www.onsemi.com
9
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(Unless otherwise stated: −10°C < T
A
< 100°C; 4.6 V < VCC < 5.4 V; C
VCC
= 0.1 mF)
Parameter UnitMaxTypMinSymbolTest Conditions
PSI
PSI High Threshold
V
IH
1.45 V
PSI Mid threshold V
MID
0.8 1 V
PSI Low threshold V
IL
0.575 V
PSI Input Leakage Current V
PSI
= 0 V I
L
−1 1
mA
PWM_VID BUFFER
Upper Threshold
V
IH
1.21 V
Lower Threshold V
IL
0.575 V
PWM_VID Switching Frequency F
PWM_VID
400 5000 kHz
Output Rise Time t
R
3 ns
Output Fall Time t
F
3 ns
Rising and Falling Edge Delay
Dt = t
R
− t
F
Dt
0.5 ns
Propagation Delay t
PD
= t
PDHL
= t
PDLH
t
PD
8 ns
Propagation Delay Error
Dt
PD
= t
PDHL
− t
PDLH
Dt
PD
0.5 ns
REFIN
REFIN Discharge Switch
ON-Resistance
I
REEFIN(SINK)
= 2 mA R
DISCH
10
W
Ratio of Output Voltage Ripple
Transferred from REFIN/REFIN
Voltage Ripple
F
PWM_VID
= 400 kHz,
F
SW
≤ 600 kHz
V
ORP/VREFIN
10
%
F
PWM_VID
= 1000 kHz,
F
SW
≤ 600 kHz
V
ORP/VREFIN
30
I
2
C
Logic High Input Voltage
V
IH
1.7 V
Logic Low Input Voltage V
IL
0.5 V
Hysteresis (Note 4) 80 mV
Output Low Voltage I
SDA
= −6 mA V
OL
0.4 V
Input Current I
L
−1 1
mA
Input Capacitance (Note 4) C
SDA
, C
SCL
5 pF
Clock Frequency
See Figure 3
f
SCL
400 kHz
SCL Low Period (Note 4) t
LOW
1.3
ms
SCL High Period (Note 4) t
HIGH
0.6
ms
SCL/SDA Rise Time (Note 4) t
R
300 ns
SCL/SDA Fall Time (Note 4) t
F
300 ns
Start Condition Setup Time
(Note 4)
t
SU;STA
600 ns
Start Condition Hold Time
(Note 1, 4)
t
HD;STA
600 ns
Data Setup Time (Note 2, 4) t
SU;DAT
100 ns
Data Hold Time (Note 2, 4) t
HD;DAT
300 ns
Stop Condition Setup Time
(Note 3, 4)
t
SU;STO
600 ns
Bus Free Time between Stop
and Start (Note 4)
t
BUF
1.3
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Time from 10% of SDA to 90% of SCL.
2. Time from 10% or 90%of SDA to 10% of SCL.
3. Time from 90% of SCL to 10% of SDA.
4. Guaranteed by design, not production tested.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

NCP81274MNTXG

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Buy NCP81274MNTXG
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers 8 PHASE CONTROLLER
Lifecycle:
New from this manufacturer.
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