NCP81274
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13
Figure 7. Ramp Feed-Forward Circuit
V
ramp_p
p
V
IN
Duty
Comp-IL
PWM Output Configuration
By default the controller operates in 8 phase mode,
however with the use of the CSP pins the phases can be
disabled by connecting the CSP pin to VCC. At power-up
the NCP81274 measures the voltage present at each CSP pin
and compares it with the phase detection threshold. If the
voltage exceeds the threshold, the phase is disabled. The
phase configurations that can be achieved by the device are
listed in Table 6. The active phase (PWM
X
) information is
also available to the user in the phase status register.
PSI, LPC
X
, PHTH
X
The NCP81274 incorporates a power saving interface
(PSI) to maximize the efficiency of the regulator under
various loading conditions. The device supports up to six
distinct operation modes, called power zones using the PSI,
LPC
X
and PHTH
X
pins (see Table 7). At power-up the
controller reads the PSI pin logic state and sources a 10 mA
current through the resistors connected to the LPC
X
and
PHTH
X
pins, measures the voltage at these pins and
configures the device accordingly.
The configuration can be changed by the user by writing
to the LPC
X
and PHTH
X
configuration registers.
After EN is set high, the NCP81274 ignores any change
in the PSI pin logic state until the output voltage reaches the
nominal regulated voltage.
When PSI = High, the controller operates with all active
phases enabled regardless of the load current. If PSI = Mid,
the NCP81274 operates in dynamic phase shedding mode
where the voltage present at the IOUT pin (the total load
current) is measured every 10 ms and compared to the
PHTH
X
thresholds to determine the appropriate power
zone.
The resistors connected between the PHTH
X
and GND
should be picked to ensure that a 10 mA current will match
the voltage drop at the IOUT pin at the desired load current.
Please note that the maximum allowable voltage at the
IOUT pin at the maximum load current is 2 V. Any PHTH
X
threshold can be disabled if the voltage drop across the
PHTH
X
resistor is 2 V for a 10 mA current, the pin is left
floating or 0xFF is written to the appropriate PHTH
X
configuration register.
At power-up, the automatic phase shedding mode is only
enabled after the output voltage reaches the nominal
regulated voltage.
When PSI = Low, the controller is set to a fixed power
zone regardless of the load current. The LPC2 setting
controls the power zone used during boot-up (after EN is set
high) while the LPC1 configuration sets the power zone
during normal operation. If PSI = Low during power-up, the
configuration set by LPC1 is activated only after PSI leaves
the low state (set to Mid or High) and set again to the low
state.
LLTH/I2C_ADD
The LLTH/I2C_ADD pin enables the user to change the
percentage of the externally programmed droop that takes
effect on the output. In addition, the LLTH/I2C_ADD pin
sets the I
2
C slave address of the NCP81274. The maximum
load line is controlled externally by setting the gain of the
current sense amplifier. On power up a 10 mA current is
sourced from the LLTH/I2C_ADD pin through a resistor
and the resulting voltage is measured. The load line and I
2
C
slave address configurations achievable using the external
resistor is listed in the table below. The percentage load line
can be fine-tuned over the I
2
C interface by writing to the LL
configuration register.
Table 5. LLTH/I2C_ADD PIN SETTING
Resistor
(kW)
Load Time
(%)
Slave Address
(Hex)
10
100 0x20
23.2 0 0x20
37.4 100 0x30
54.9 0 0x30
78.7 100 0x40
110 0 0x40
147 100 0x50
249 0 0x50
NOTE: 1% tolerance.
NCP81274
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14
Table 6. PWM OUTPUT CONFIGURATION
Configuration
Phase
Configuration
CSP Pin Configuration
(3 = Normal Connection, X = Tied to VCC)
Enabled
PWM Outputs
(PWM
X
Pins)
CSP1 CSP2 CSP3 CSP4 CSP5 CSP6 CSP7 CSP8
1 8 Phase
3 3 3 3 3 3 3 3
1, 2, 3, 4, 5, 6, 7, 8
2 7 Phase
3 3 3 3 3 3 3
X 1, 2, 3, 4, 5, 6, 7
3 6 Phase
3 3 3 3 3 3
X X 1, 2, 3, 4, 5, 6
4 5 Phase
3 3 3 3 3
X X X 1, 2, 3, 4, 5
5 4 Phase
3 3 3 3
X X X X 1, 2, 3, 4
6 3 Phase
3 3 3
X X X X X 1, 2, 3
7 2 Phase
3 3
X X X X X X 1, 2
8 1 Phase
3
X X X X X X X 1
Table 7. PSI, LPC
X
, PHTH
X
CONFIGURATION (Note 1)
PSI
Logic
State
LPC
X
Resistor
(kW)
IOUT vs. PHTH
X
Comparison
Power Zone (Note 2)
8
Phase
7
Phase
6
Phase
5
Phase
4
Phase
3
Phase
2
Phase
1
Phase
High Disabled
Function Disabled
0 0 0 0 0 0 0 0
Low
10 0 0 0 0 0 0 0 0
23.2 1 0 0 0 0 0 0 0
37.4 2 0 2 0 2 0 0 0
54.9 3 3 3 3 3 3 3 0
78.7 4 4 4 4 4 4 4 4
Mid Function
Disabled
IOUT > PHTH4 0 0 0 0 0 0 0 0
PTHT4 > IOUT > PHTH3 1 0 0 0 0 0 0 0
PHTH3 > IOUT > PHTH2 2 0 2 0 2 0 0 0
PHTH2 > IOUT > PHTH1 3 3 3 3 3 3 3 0
IOUT < PHTH1 4 4 4 4 4 4 4 4
1. 1% tolerance.
2. Power zone 4 is DCM @100 kHz switching frequency, while zones 0 to 3 are CCM.
Table 8. PHASE SHEDDING CONFIGURATIONS
Power Zone
PWM Output Configuration
PWM Output Status (3 = Enabled, X = Disabled)
PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8
0
8 Phase
3 3 3 3 3 3 3 3
1
3
X
3
X
3
X
3
X
2
3
X X X
3
X X X
3
3
X X X X X X X
4
3
X X X X X X X
0
7 Phase
3 3 3 3 3 3 3
X
3
3
X X X X X X X
4
3
X X X X X X X
0
6 Phase
3 3 3 3 3 3
X X
2
3
X
3
X
3
X X X
3
3
X X X X X X X
4
3
X X X X X X X
NCP81274
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Table 8. PHASE SHEDDING CONFIGURATIONS (continued)
Power Zone
PWM Output Status (3 = Enabled, X = Disabled)
PWM Output Configuration
Power Zone
PWM8PWM7PWM6PWM5PWM4PWM3PWM2PWM1
PWM Output Configuration
0
5 Phase
3 3 3 3 3
X X X
3
3
X X X X X X X
4
3
X X X X X X X
0
4 Phase
3 3 3 3
X X X X
2
3
X
3
X X X X X
3
3
X X X X X X X
4
3
X X X X X X X
0
3 Phase
3 3 3
X X X X X
3
3
X X X X X X X
4
3
X X X X X X X
0
2 Phase
3 3
X X X X X X
3
3
X X X X X X X
4
3
X X X X X X X
0
1 Phase
3
X X X X X X X
4
3
X X X X X X X
Power Zone Transition/Phase Shedding
The power zones supported by the NCP81274 are set by
the resistors connected to the LPC
X
pins (PSI = Low) or
PHTH
X
pins (PSI = Mid).
When PSI is set to the Mid-state, the NCP81274 employs
a phase shedding scheme where the power zone is
automatically adjusted for optimal efficiency by
continuously measuring the total output current (voltage at
the IOUT pin) and compare it with the PHTH
X
thresholds.
When the comparison result indicates that a lower power
zone number is required (an increase in the IOUT value), the
controller jumps to the required power zone immediately.
A decrease in IOUT that indicates that the controller needs
to switch into a higher power zone number, the transition
will be executed with a delay of 200 ms set by the phase shed
delay configuration register. The value of the delay can be
adjusted by the user in steps of 10 ms if required. To avoid
excessive ripple on the output voltage, all power zone
changes are gradual and include all intermediate power
zones between the current zone and the target zone set by the
comparison of the output current with the PHTH
X
thresholds, each transition introducing a programmable
200 ms delay. To avoid false changes from one power zone
to another caused by noise or short IOUT transients, the
comparison between IOUT and PHTH
X
threshold uses
hysteresis. The switch to a lower power zone is executed if
IOUT exceeds the PHTH
X
threshold values while
a transition to a higher power zone number is only executed
if IOUT is below PHTH
X
-Hysteresis value. The hysteresis
value is set to 0x10h and can be changed by the user by
writing to the phase shedding configuration register. If
a power zone/PHTH
X
threshold is disabled, the controller
will skip it during the power zone transition process.
When PSI = Low and the user requires to change the
power zone, the transition to the new power zone is identical
to the transition process used when PSI is set to the
Mid-state. The only exception is when the target power zone
is disabled in automatic phase shedding mode. In this case,
the controller will automatically enable the target power
zone and allow the transition. When the controller is set to
automatic phase shedding, the power zone will be
automatically disabled.
Switching Frequency
A programmable precision oscillator is provided. The
clock oscillator serves as the master clock to the ramp
generator circuit. This oscillator is programmed by a resistor
to ground on the FSW pin. The FSW pin provides
approximately 2 V out and the source current is mirrored
into the internal ramp oscillator. The oscillator frequency is
approximately proportional to the current flowing in the
resistor. Table 19 lists the switching frequencies that can be
set using discrete resistor values for each phase
configuration. Also, the switching frequency information is
available in the FSW configuration register and it can be
changed by the user by writing to the FSW configuration
register.
Total Current Sense Amplifier
The controller uses a patented approach to sum the phase
currents into a single temperature compensated total current
signal (Figure 8).
This signal is then used to generate the output voltage
droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to
CSREF. The current signal is the difference between

NCP81274MNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers 8 PHASE CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
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