PIC18F25J50-I/SS Datasheet PIC18F25J50-I/SS, PIC18F26J50-I/ML, PIC18F26J50-I/SO | P22-P24

PIC18F2XJXX/4XJXX FAMILY

DS30009687F-page 22  2008-2015 Microchip Technology Inc.

DSWTPS<3:0> CONFIG3L Deep Sleep Watchdog Timer Postscale Select bits

The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.

1111 = 1:2,147,483,648 (25.7 days)

1110 = 1:536,870,912 (6.4 days)

1101 = 1:134,217,728 (38.5 hours)

1100 = 1:33,554,432 (9.6 hours)

1011 = 1:8,388,608 (2.4 hours)

1010 = 1:2,097,152 (36 minutes)

1001 = 1:524,288 (9 minutes)

1000 = 1:131,072 (135 seconds)

0111 = 1:32,768 (34 seconds)

0110 = 1:8,192 (8.5 seconds)

0101 = 1:2,048 (2.1 seconds)

0100 = 1:512 (528 ms)

0011 = 1:128 (132 ms)

0010 = 1:32 (33 ms)

0001 = 1:8 (8.3 ms)

0000 = 1:2 (2.1 ms)

DSWDTEN CONFIG3L Deep Sleep Watchdog Timer Enable bit

1 = DSWDT enabled

0 = DSWDT disabled

DSBOREN CONFIG3L Deep Sleep BOR Enable bit

1 = BOR enabled in Deep Sleep

0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)

RTCOSC CONFIG3L RTCC Reference Clock Select bit

1 = RTCC uses T1OSC/T1CKI as reference clock

0 = RTCC uses INTRC as reference clock

DSWDTOSC CONFIG3L DSWDT Reference Clock Select bit

1 = DSWDT uses INTRC as reference clock

0 = DSWDT uses T1OSC/T1CKI as reference clock

MSSPMSK

(1,2)

CONFIG3H MSSP 7-Bit Address Masking Mode Enable bit

1 = 7-Bit Address Masking mode enable

0 = 5-Bit Address Masking mode enable

IOL1WAY CONFIG3H IOLOCK Bit One-Way Set Enable bit

1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has

been completed. Once set, the Peripheral Pin Select registers cannot be written to a

second time.

0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the

unlock sequence has been completed.

WPCFG

(4)

CONFIG4L Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)

1 = Configuration Words page is not erase/write-protected unless WPEND and

WPFP<5:0> settings include the Configuration Words page

0 = Configuration Words page is erase/write-protected, regardless of WPEND and

WPFP<5:0> settings

WPEND CONFIG4L Write/Erase Protect Region Select bit (valid when WPDIS = 0)

1 = Flash pages, WPFP<5:0> to Configuration Words page, are write/erase-protected

0 = Flash pages, 0 to WPFP<5:0> are write/erase-protected

TABLE 5-5: PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)

Bit Name

Configuration

Words

Description

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on V

DD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F46J11 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP™ Bulk Erase operation.

 2008-2015 Microchip Technology Inc. DS30009687F-page 23

PIC18F2XJXX/4XJXX FAMILY

TABLE 5-6: PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: CONFIGURATION BITS AND

DEVICE IDs

WPFP<5:0> CONFIG4L Write/Erase Protect Page Start/End Location bits

Used with WPEND bit to define which pages in Flash will be write/erase-protected.

WPDIS CONFIG4H Write Protect Disable bit

1 = WPFP<5:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or

written

0 = WPFP<5:0>, WPEND and WPCFG bits enabled; write/erase-protect active for the

selected region(s)

DEV<2:0> DEVID1 Device ID bits

Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number.

REV<4:0> DEVID1 Revision ID bits

Indicate the device revision.

DEV<10:3> DEVID2 Device ID bits

Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default/

Unprogrammed

Value

(1)

300000h CONFIG1L DEBUG XINST STVREN CFGPLLEN PLLDIV2 PLLDIV1 PLLDIV0 WDTEN 111- 1111

300001h CONFIG1H

—

(2)

—

(2)

—

(2)

—

(2)

—

(4)

CP0 CPDIV1

(3)

CPDIV0

(3)

---- 0111

300002h CONFIG2L IESO FCMEN CLKOEC SOSCSEL1 SOSCSEL0 FOSC2 FOSC1 FOSC0 1111 1111

300003h CONFIG2H

—

(2)

—

(2)

—

(2)

—

(2)

WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111

300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN RTCOSC DSWDTOSC 1111 1111

300005h CONFIG3H

—

(2)

—

(2)

—

(2)

—

(2)

MSSPMSK PLLSEL ADCSEL IOL1WAY ---- 1111

300006h CONFIG4L WPCFG WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 1111 1111

300007h CONFIG4H

—

(2)

—

(2)

—

(2)

—

(2)

LS48MHZ

(3)

— WPEND WPDIS ---- 1-11

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx

3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0101 10xx

Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the

configuration bytes maintain their previously programmed states.

2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is

accidentally executed.

3: These bits are not implemented in PIC18F47J13 family devices.

4: This bit should always be maintained at ‘0’.

TABLE 5-5: PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)

Bit Name

Configuration

Words

Description

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on V

DD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F46J11 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP™ Bulk Erase operation.

PIC18F2XJXX/4XJXX FAMILY

DS30009687F-page 24  2008-2015 Microchip Technology Inc.

TABLE 5-7: PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS

Bit Name

Configuration

Words

Description

DEBUG

CONFIG1L Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general purpose

I/O pins

0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug

XINST CONFIG1L Enhanced Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

STVREN CONFIG1L Stack Overflow/Underflow Reset Enable bit

1 = Reset on stack overflow/underflow enabled

0 = Reset on stack overflow/underflow disabled

CFGPLLEN CONFIG1L Enable PLL on Start-up bit

1 = PLL enabled on start-up. Not recommended for low-voltage designs.

0 = PLL disabled on start-up. Firmware may later enable PLL through OSCTUNE<6>.

PLLDIV<2:0> CONFIG1L 96 MHz PLL Input Divider bits

Divider must be selected to provide a 4 MHz input into the 96 MHz PLL.

111 =No divide – oscillator used directly (4 MHz input)

110 =Oscillator divided by 2 (8 MHz input)

101 =Oscillator divided by 3 (12 MHz input)

100 =Oscillator divided by 4 (16 MHz input)

011 =Oscillator divided by 5 (20 MHz input)

010 =Oscillator divided by 6 (24 MHz input)

001 =Oscillator divided by 10 (40 MHz input)

000 =Oscillator divided by 12 (48 MHz input)

WDTEN CONFIG1L Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on the SWDTEN bit)

CP0

(4)

CONFIG1H Code Protection bit

1 = Program memory is not code-protected

0 = Program memory is code-protected

CPDIV<1:0>

(3)

CONFIG1H CPU System Clock Selection bits

11 = No CPU system clock divide

10 = CPU system clock divided by 2

01 = CPU system clock divided by 3

00 = CPU system clock divided by 6

IESO CONFIG2L

(1,2)

Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit

1 = Oscillator Switchover mode enabled

0 = Oscillator Switchover mode disabled

FCMEN CONFIG2L

(1,2)

Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

CLKOEC CONFIG2L EC Mode Clock Output Enable bit

1 = CLKO output signal active on the RA6 pin (EC mode only)

0 = CLKO output disabled

SOSCSEL<1:0> CONFIG2L Secondary Oscillator Circuit Selection bits

11 = High-power SOSC circuit selected

10 = Digital Input mode (SCLKI)

01 = Low-power SOSC circuit selected

00 = Reserved

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on V

DD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F47J13 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP™ Bulk Erase operation.

5: Not implemented on PIC18F47J53 family devices.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

PIC18F25J50-I/SS

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Description:

8-bit Microcontrollers - MCU Full Spd USB 32KB Flsh 4KBRAM nanoWatt

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