PIC18F25J50-I/SS Datasheet PIC18F25J50-I/SS, PIC18F26J50-I/ML, PIC18F26J50-I/SO | P25-P27

 2008-2015 Microchip Technology Inc. DS30009687F-page 25

PIC18F2XJXX/4XJXX FAMILY

FOSC<2:0> CONFIG2L

(1,2)

Oscillator Selection bits

111 =EC+PLL (S/W controlled by PLLEN bit), CLKO on RA6

110 =EC oscillator (PLL always disabled) with CLKO on RA6

101 =HS+PLL (S/W controlled by PLLEN bit)

100 =HS oscillator (PLL always disabled)

011 =INTOSCPLLO, internal oscillator with PLL (S/W controlled by PLLEN bit), CLKO on

RA6, port function on RA7

010 =INTOSCPLL, internal oscillator with PLL (S/W controlled by PLLEN bit), port

function on RA6 and RA7

001 =INTOSCO, internal oscillator, INTOSC or INTRC (PLL always disabled), CLKO on

RA6, port function on RA7

000 =INTOSC, internal oscillator INTOSC or INTRC (PLL always disabled), port function

on RA6 and RA7

WDTPS<3:0> CONFIG2H

(1,2)

Watchdog Timer Postscale Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

DSWTPS<3:0> CONFIG3L Deep Sleep Watchdog Timer Postscale Select bits

The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.

1111 = 1:2,147,483,648 (25.7 days)

1110 = 1:536,870,912 (6.4 days)

1101 = 1:134,217,728 (38.5 hours)

1100 = 1:33,554,432 (9.6 hours)

1011 = 1:8,388,608 (2.4 hours)

1010 = 1:2,097,152 (36 minutes)

1001 = 1:524,288 (9 minutes)

1000 = 1:131,072 (135 seconds)

0111 = 1:32,768 (34 seconds)

0110 = 1:8,192 (8.5 seconds)

0101 = 1:2,048 (2.1 seconds)

0100 = 1:512 (528 ms)

0011 = 1:128 (132 ms)

0010 = 1:32 (33 ms)

0001 = 1:8 (8.3 ms)

0000 = 1:2 (2.1 ms)

DSWDTEN CONFIG3L Deep Sleep Watchdog Timer Enable bit

1 = DSWDT enabled

0 = DSWDT disabled

DSBOREN CONFIG3L Deep Sleep BOR Enable bit

1 = BOR enabled in Deep Sleep

0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)

TABLE 5-7: PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)

Bit Name

Configuration

Words

Description

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on V

DD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F47J13 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP™ Bulk Erase operation.

5: Not implemented on PIC18F47J53 family devices.

PIC18F2XJXX/4XJXX FAMILY

DS30009687F-page 26  2008-2015 Microchip Technology Inc.

RTCOSC CONFIG3L RTCC Reference Clock Select bit

1 = RTCC uses T1OSC/T1CKI as reference clock

0 = RTCC uses INTRC as reference clock

DSWDTOSC CONFIG3L DSWDT Reference Clock Select bit

1 = DSWDT uses INTRC as reference clock

0 = DSWDT uses T1OSC/T1CKI as reference clock

MSSPMSK

(1,2)

CONFIG3H MSSP 7-Bit Address Masking Mode Enable bit

1 = 7-Bit Address Masking mode enable

0 = 5-Bit Address Masking mode enable

PLLSEL

(5)

CONFIG3H PLL Selection bit

1 = 4x PLL selected

0 = 96 MHz PLL selected

ADCSEL CONFIG3H ADC Mode Selection bit

1 = 10-Bit ADC mode selected

0 = 12-Bit ADC mode selected

IOL1WAY CONFIG3H IOLOCK Bit One-Way Set Enable bit

1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has

been completed. Once set, the Peripheral Pin Select registers cannot be written to a

second time.

0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the

unlock sequence has been completed

WPCFG CONFIG4L Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)

1 = Configuration Words page is not erase/write-protected unless WPEND and

WPFP<6:0> settings include the Configuration Words page

0 = Configuration Words page is erase/write-protected, regardless of WPEND and

WPFP<6:0>

WPFP<6:0> CONFIG4L Write/Erase Protect Page Start/End Location bits

Used with WPEND bit to define which pages in Flash will be write/erase-protected.

WPEND CONFIG4H Write/Erase Protect Region Select bit (valid when WPDIS = 0)

1 = Flash pages, WPFP<6:0> to Configuration Words page, are write/erase-protected

0 = Flash pages, 0 to WPFP<6:0> are write/erase-protected

WPDIS CONFIG4H Write Protect Disable bit

1 = WPFP<6:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or

written

0 = WPFP<6:0>, WPEND and WPCFG bits enabled; write/erase-protect active for the

selected region(s)

LS48MHZ

(3)

CONFIG4H System Clock Selection bit

1 = System clock is expected at 48 MHz, FS/LS USB CLKEN’s divide-by is set to 8

0 = System clock is expected at 24 MHz, FS/LS USB CLKEN’s divide-by is set to 4

DEV<2:0> DEVID1 Device ID bits

Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number.

REV<4:0> DEVID1 Revision ID bits

Indicate the device revision.

DEV<10:3> DEVID2 Device ID bits

Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.

TABLE 5-7: PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)

Bit Name

Configuration

Words

Description

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on V

DD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F47J13 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP™ Bulk Erase operation.

5: Not implemented on PIC18F47J53 family devices.

 2008-2015 Microchip Technology Inc. DS30009687F-page 27

PIC18F2XJXX/4XJXX FAMILY

5.1 Device ID Word

The Device ID Word for the PIC18F2XJXX/4XJXX

Family devices is located at 3FFFFEh:3FFFFFh.

These read-only bits may be used by the programmer

to identify what device type is being programmed and

read out normally, even after code protection has been

enabled. The process for reading the Device IDs is

shown in Figure 5-1. A complete list of Device ID

values for the PIC18F2XJXX/4XJXX Family is

presented in Table 5-8.

FIGURE 5-1: READ DEVICE ID WORD FLOW

5.2 Checksum Computation

The checksum is calculated by summing the contents of

all code memory locations and the device Configuration

Words, appropriately masked. The Least Significant

16 bits of this sum are the checksum.

The checksum calculation differs depending on

whether or not code protection is enabled. Since the

code memory locations read out differently depending

on the code-protect setting, the table describes how to

manipulate the actual code memory values to simulate

the values that would be read from a protected device.

When calculating a checksum by reading a device, the

entire code memory can simply be read and summed.

The Configuration Words can always be read.

TABLE 5-8: DEVICE ID VALUE

Device

Device ID Value

DEVID2 DEVID1

PIC18F24J10 1Dh 000x xxxx

PIC18F25J10 1Ch 000x xxxx

PIC18F44J10 1Dh 001x xxxx

PIC18F45J10 1Ch 001x xxxx

PIC18LF24J10 1Dh 010x xxxx

PIC18LF25J10 1Ch 010x xxxx

PIC18LF44J10 1Dh 011x xxxx

PIC18LF45J10 1Ch 011x xxxx

PIC18F25J11 4Dh 101x xxxx

PIC18F24J11 4Dh 100x xxxx

PIC18F26J11 4Dh 110x xxxx

PIC18F45J11 4Eh 000x xxxx

PIC18F44J11 4Dh 111x xxxx

PIC18F46J11 4Eh 001x xxxx

PIC18F24J50 4Ch 000x xxxx

PIC18F25J50 4Ch 001x xxxx

PIC18F26J50 4Ch 010x xxxx

PIC18F44J50 4Ch 011x xxxx

PIC18F45J50 4Ch 100x xxxx

Start

Set TBLPTR = 3FFFFE

Done

Read Low Byte

Read High Byte

with Post-Increment

PIC18F46J50 4Ch 101x xxxx

PIC18LF2450 4Ch 110x xxxx

PIC18LF25J50 4Ch 111x xxxx

PIC18LF26J50 4Dh 000x xxxx

PIC18LF44J50 4Dh 001x xxxx

PIC18LF45J50 4Dh 010x xxxx

PIC18LF46J50 4Dh 011x xxxx

PIC18LF24J11 4Eh 010x xxxx

PIC18LF25J11 4Eh 011x xxxx

PIC18LF26J11 4Eh 100x xxxx

PIC18LF44J11 4Eh 101x xxxx

PIC18LF45J11 4Eh 110x xxxx

PIC18LF46J11 4Eh 111x xxxx

PIC18F26J13 59h 001x xxxx

PIC18F27J13 59h 011x xxxx

PIC18F46J13 59h 101x xxxx

PIC18F47J13 59h 111x xxxx

PIC18LF26J13 5Bh 001x xxxx

PIC18LF27J13 5Bh 011x xxxx

PIC18LF46J13 5Bh 101x xxxx

PIC18LF47J13 5Bh 111x xxxx

PIC18F26J53 58h 001x xxxx

PIC18F27J53 58h 011x xxxx

PIC18F46J53 58h 101x xxxx

PIC18F47J53 58h 111x xxxx

PIC18LF26J53 5Ah 001x xxxx

PIC18LF27J53 5Ah 011x xxxx

PIC18LF46J53 5Ah 101x xxxx

PIC18LF47J53 5Ah 111x xxxx

TABLE 5-8: DEVICE ID VALUE (CONTINUED)

Device

Device ID Value

DEVID2 DEVID1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

PIC18F25J50-I/SS

Mfr. #:

Buy PIC18F25J50-I/SS

Manufacturer:

Microchip Technology

Description:

8-bit Microcontrollers - MCU Full Spd USB 32KB Flsh 4KBRAM nanoWatt

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

PIC18F25J50-I/SS

PIC18F25J50-I/SS

Products related to this Datasheet