PIC18F2XJXX/4XJXX FAMILY
DS30009687F-page 4 2008-2015 Microchip Technology Inc.
2.1.1 PIC18F2XJXX/4XJXX/
LF2XJXX/LF4XJXX DEVICES AND
THE ON-CHIP VOLTAGE
REGULATOR
PIC18FXXJXX devices have an internal core voltage
regulator. On these devices (“PIC18F” in the part num-
ber), the regulator is always enabled. The regulator
input is taken from the V
DD pins of the microcontroller.
The output of the regulator is supplied to the V
DDCORE/
V
CAP pin. On these devices, this pin simultaneously
serves as both regulator output and microcontroller
core power input pin. For these devices, the VDDCORE/
V
CAP pin should be tied only to a capacitor.
PIC18LFXXJXX devices do not have an internal core
voltage regulator. On the low-voltage devices (LF),
power must be externally supplied to both V
DD and
V
DDCORE/VCAP.
Whether or not the regulator is used, it is always good
design practice to have sufficient capacitance on all
supply pins. Examples are shown in Figure 2-3.
The specifications for core voltage and capacitance are
listed in Section 6.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode”.
FIGURE 2-3: CONNECTIONS FOR THE
ON-CHIP REGULATOR
2.2 Memory Maps
The PIC18F2XJXX/4XJXX Family of devices offers
program memory sizes of 16, 32, 64, and 128 Kbytes.
The memory sizes for different members of the family
are shown in Table 2-2. The overall memory maps for
all the devices are shown in Figure 2-4.
TABLE 2-2: PROGRAM MEMORY SIZES
FOR PIC18F2XJXX/4XJXX
FAMILY DEVICES
For purposes of code protection, the program memory
for every device is treated as a single block. Therefore,
enabling code protection, thus protecting the entire
code memory and not individual segments.
2.5V
VDD
VDDCORE/VCAP
VSS
2.5V
VDD
VDDCORE/VCAP
VSS
3.3V
(V
DD VDDCORE)
(V
DD VDDCORE)
PIC18F2XJXX/4XJXX Devices (Regulator Enabled)
PIC18F2XJXX/4XJXX
PIC18LF2XJXX/4XJXX Devices (Regulator Disabled)
V
DD
V
DDCORE
/V
CAP
V
SS
CF
3.3V
PIC18LF2XJXX/4XJXX
PIC18LF2XJXX/4XJXX
Device*
Program
Memory
(Kbytes)
Location of Flash
Configuration
Words
PIC18F24J10
16 3FF8h:3FFFh
PIC18F44J10
PIC18F24J11
PIC18F44J11
PIC18F24J50
PIC18F44J50
PIC18F25J10
32 7FF8h:7FFFh
PIC18F45J10
PIC18F25J11
PIC18F45J11
PIC18F25J50
PIC18F45J50
PIC18F26J11
64 FFF8h:FFFFh
PIC18F46J11
PIC18F26J13
PIC18F46J13
PIC18F26J50
PIC18F46J50
PIC18F26J53
PIC18F46J53
PIC18F27J13
128 1FFF8h:1FFFFh
PIC18F47J13
PIC18F27J53
PIC18F47J53
* Includes PIC18F and PIC18LF devices.
2008-2015 Microchip Technology Inc. DS30009687F-page 5
PIC18F2XJXX/4XJXX FAMILY
The Configuration Words for these devices are located
at addresses 300000h through 300007h. These are
implemented as three pairs of volatile memory
registers. Each register is automatically loaded from a
copy stored at the end of program memory. For this
reason, the last four words (or eight bytes) of the code
space (also called the Flash Configuration Words)
should be written with Configuration data and not
executable code. The addresses of the Flash
Configuration Words are listed in Table 2-2. Refer to
section Section 5.0 “Configuration Word” for more
information.
Locations 3FFFFEh and 3FFFFFh are reserved for the
Device ID bits. These bits, which may be used by the
programmer to identify what device type is being pro-
grammed, are described in Section 5.1 “Device ID
Word. These Device ID bits read out normally, even
after code protection.
2.2.1 MEMORY ADDRESS POINTER
Memory in the device address space (000000h to
3FFFFFh) is addressed via the Table Pointer register,
which in turn is comprised of three registers:
TBLPTRU at RAM address 0FF8h
TBLPTRH at RAM address 0FF7h
TBLPTRL at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
PIC18F2XJXX/4XJXX FAMILY
DS30009687F-page 6 2008-2015 Microchip Technology Inc.
FIGURE 2-4: MEMORY MAPS FOR PIC18F2XJXX/4XJXX FAMILY DEVICES
(1)
Note 1: Sizes of memory areas are not to scale. Sizes of accessible memory areas are enhanced to show detail.
2: Addresses 300006h and 300007h are unimplemented in PIC18F45J10 Family devices.
Code Memory
Unimplemented
Read as0
Configuration
Space
000000h
1FFFFFh
3FFFFFh
2FFFFFh
003FFFh
007FFFh
200000h
300000h
300007h
(2)
3FFFFEh
Configuration
Words
Device IDs
Configuration
Space
Memory spaces are unimplemented or unavailable in normal execution mode and read as ‘0’.
Memory spaces are read-only (Device IDs) or cannot be directly programmed by ICSP™ (Configuration Words).
Flash Conf. Words
PIC18FX4JXX
(16 Kbytes)
Code Memory
Unimplemented
Read as ‘0
Configuration
Space
Configuration
Words
Device IDs
Configuration
Space
Flash Conf. Words
PIC18FX6JXX
(64 Kbytes)
Code Memory
Unimplemented
Read as ‘0
Configuration
Space
Configuration
Words
Device IDs
Configuration
Space
Flash Conf. Words
PIC18FX5JXX
(32 Kbytes)
Code Memory
Unimplemented
Read as0
Configuration
Space
Configuration
Words
Device IDs
Configuration
Space
Flash Conf. Words
PIC18FX7JXX
(128 Kbytes)
01FFFFh
00FFFFh

PIC18F25J50-I/SS

Mfr. #:
Manufacturer:
Microchip Technology
Description:
8-bit Microcontrollers - MCU Full Spd USB 32KB Flsh 4KBRAM nanoWatt
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union