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PIC18F25J50-I/SS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
PIC18F2XJXX/4XJXX FAMILY
DS30009687F-page 28 2008-2015 Microchip Technology Inc.
Table 5-9 describes how to calculate the checksum for
each device.
TABLE 5-9: CHECKSUM COMPUTATION
Device
Code
Protection
Checksum
PIC18F24J10
PIC18F44J10
Off
SUM[000000:003FF7] + ([003FF8] & E1h) + ([003FF9] & 04h) + ([003FFA] & C7h) +
([003FFB] & 0Fh) + ([003FFD] & 01h)
On 0000h
PIC18F24J11
PIC18F44J11
Off
SUM[000000:003FF7] + ([003FF8] & E1h) + ([003FF9] & FCh) + ([003FFA] & DFh) +
([003FFB] & FFh) + ([003FFC] & FFh) + ([003FFD] & F9h) + ([003FFE] & FFh) +
([003FFF] & F1h)
On 0000h
PIC18F24J50
PIC18F44J50
Off
SUM[000000:003FF7] + ([003FF8] & EFh) + ([003FF9] & FFh) + ([003FFA] & DFh) +
([003FFB] & FFh) + ([003FFC] & FFh) + ([003FFD] & F9h) + ([003FFE] & FFh) +
([003FFF] & F1h)
On 0000h
PIC18F25J10
PIC18F45J10
Off
SUM[000000:007FF7] + ([007FF8] & E1h) + ([007FF9] & 04h) + ([007FFA] & C7h) +
([007FFB] & 0Fh) + ([007FFD] & 01h)
On 0000h
PIC18F25J11
PIC18F45J11
Off
SUM[000000:007FF7] + ([007FF8] & E1h) + ([007FF9] & FCh) + ([007FFA] & DFh) +
([007FFB] & FFh) + ([007FFC] & FFh) + ([007FFD] & F9h) + ([007FFE] & FFh) +
([007FFF] & F1h)
On 0000h
PIC18F25J50
PIC18F45J50
Off
SUM[000000:007FF7] + ([007FF8] & EFh) + ([007FF9] & FFh) + ([007FFA] & DFh) +
([007FFB] & FFh) + ([007FFC] & FFh) + ([007FFD] & F9h) + ([007FFE] & FFh) +
([007FFF] & F1h)
On 0000h
PIC18F26J11
PIC18F46J11
Off
SUM[000000:00FFF7] + ([00FFF8] & E1h) + ([00FFF9] & FCh) + ([00FFFA] & DFh) +
([00FFFB] & FFh) + ([00FFFC] & FFh) + ([00FFFD] & F9h) + ([00FFFE] & FFh) +
([00FFFF] & F1h)
On 0000h
PIC18F26J50
PIC18F46J50
Off
SUM[000000:00FFF7] + ([00FFF8] & EFh) + ([00FFF9] & FFh) + ([00FFFA] & DFh) +
([00FFFB] & FFh) + ([00FFFC] & FFh) + ([00FFFD] & F9h) + ([00FFFE] & FFh) +
([00FFFF] & F1h)
On 0000h
PIC18F26J13
PIC18F46J13
Off
SUM[000000:00FFF7] + ([00FFF8] & FFh) + ([00FFF9] & FCh) +([00FFFA] & FFh) +
([00FFFB] & FFh) + ([00FFFC] & FFh) + ([00FFFD] & FFh) + ([00FFFE] & BFh) +
([00FFFF] & F3h)
On 0000h
PIC18F26J53
PIC18F46J53
Off
SUM[000000:00FFF7] + ([00FFF8] & FFh) + ([00FFF9] & FFh) +([00FFFA] & FFh) +
([00FFFB] & FFh) + ([00FFFC] & FFh) + ([00FFFD] & FBh) + ([00FFFE] & BFh) +
([00FFFF] & FBh)
On 0000h
PIC18F27J13
PIC18F47J13
Off
SUM[000000:01FFF7] + ([01FFF8] & FFh) + ([01FFF9] & FCh) + ([01FFFA] & FFh) +
([01FFFB] & FFh) + ([01FFFC] & FFh) + ([01FFFD] & FFh) + ([01FFFE] & FFh) +
([01FFFF] & F3h)
On 0000h
PIC18F27J53
PIC18F47J53
Off
SUM[000000:01FFF7] + ([01FFF8] & FFh) + ([01FFF9] & FFh) + ([01FFFA] & FFh) +
([01FFFB] & FFh) + ([01FFFC] & FFh) + ([01FFFD] & FBh) + ([01FFFE] & FFh) +
([01FFFF] & FBh)
On 0000h
Legend: [a] = Value at address a; SUM[a:b] = Sum of locations a to b inclusive; + = Addition; & = Bitwise AND.
All addresses are hexadecimal.
2008-2015 Microchip Technology Inc. DS30009687F-page 29
PIC18F2XJXX/4XJXX FAMILY
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Symbol Characteristic Min. Max. Units Conditions
V
DDCORE External Supply Voltage for Microcontroller
Core During Programming Operations
(PIC18LF devices)
2.25 2.75 V (Note 1)
D111 V
DD Supply Voltage During
Programming
PIC18LFXXJXX VDDCORE 3.60 V Normal programming
(Note 2)
PIC18FXXJ10 2.70 3.60 V
PIC18FXXJ50
PIC18FXXJ11
PIC18FXXJ53
PIC18FXXJ13
2.35 3.60 V
D112 I
PP Programming Current on MCLR —5A
D113 I
DDP Supply Current During Programming — 10 mA
D031 VIL Input Low Voltage VSS 0.2 VDD V
D041 V
IH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.4 V IOL = 3.4 mA @ 3.3V
D090 V
OH Output High Voltage 2.4 — V IOH = -2.0 mA @ 3.3V
D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specifications
C
F Filter Capacitor Value on
V
CAP
PIC18LFXXJXX 0.1 — F (Note 1)
PIC18FXXJ10 4.7 18 F
PIC18FXXJ13
PIC18FXXJ11
PIC18FXXJ5X
5.4 18 F
Note 1: External power must be supplied to the V
DDCORE/VCAP pin if the on-chip voltage regulator is disabled. See
Section 2.1.1 “PIC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator” for
more information.
2: V
DD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of V
DD and VSS, respectively.
PIC18F2XJXX/4XJXX FAMILY
DS30009687F-page 30 2008-2015 Microchip Technology Inc.
P1 TR MCLR Rise Time to Enter Program/Verify
mode
—1.0s
P2 T
PGC Serial Clock (PGC) Period 100 — ns
P2A T
PGCL Serial Clock (PGC) Low Time 50 — ns
P2B T
PGCH Serial Clock (PGC) High Time 50 — ns
P3 T
SET1 Input Data Setup Time to Serial Clock 20 — ns
P4 T
HLD1 Input Data Hold Time from PGC 20 — ns
P5 TDLY1 Delay Between 4-Bit Command and
Command Operand
50 — ns
P5A T
DLY1A Delay Between 4-Bit Command Operand and
Next 4-Bit Command
50 — ns
P6 T
DLY2 Delay Between Last PGC of Command
Byte to First PGC of Read of Data Word
20 — ns
P9 T
DLY5 Delay to allow Block Programming to occur 3.4 — ms PIC18F2XJ10/PIC18F4XJ10
1.2 — ms PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ5X/PIC18F4XJ5X
P10 T
DLY6 Delay to allow Row Erase to occur 49 — ms PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
54 — ms PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P11 T
DLY7 Delay to allow Bulk Erase to occur 475 — ms PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
524 — ms PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P12 T
HLD2 Input Data Hold Time from MCLR 400 — s
P13 T
SET2VDD Setup Time to MCLR 100 — ns
P14 T
VALID Data Out Valid from PGC 25 — ns
P16 T
DLY8 Delay between Last PGC and MCLR 20 — ns
P17 T
HLD3MCLR to VDD 3—s
P19 T
KEY1 Delay from First MCLR to First PGC for
Key Sequence on PGD
4—ms
P20 T
KEY2 Delay from Last PGC for Key Sequence on
PGD to Second MCLR

50 — ns
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Symbol Characteristic Min. Max. Units Conditions
Note 1: External power must be supplied to the V
DDCORE/VCAP pin if the on-chip voltage regulator is disabled. See
Section 2.1.1 “PIC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator” for
more information.
2: V
DD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of V
DD and VSS, respectively.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

PIC18F25J50-I/SS

Mfr. #:
Buy PIC18F25J50-I/SS
Manufacturer:
Microchip Technology
Description:
8-bit Microcontrollers - MCU Full Spd USB 32KB Flsh 4KBRAM nanoWatt
Lifecycle:
New from this manufacturer.
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