OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SC18IM700IPW/S8HP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 13 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
Remark: The numbers used in the formulas are in decimal, but the numbers to program
I2CClkH and I2CClkL are in hex.
9.2.6 I
2
C-bus time-out (I2CTO)
The time-out register is used to determine the maximum time that SCL is allowed to be
LOW before the I
2
C-bus state machine is reset.
When the I
2
C-bus interface is running, I2CTO is loaded after each I
2
C-bus state transition.
The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1
will enable the time-out function. The time-out period can be calculated as follows:
(3)
The time-out value may vary, and it is an approximate value.
9.2.7 I
2
C-bus status register (I2CStat)
This register reports the I
2
C-bus transmit and receive frame status, whether the frame
transmits correctly or not.
Table 8. I
2
C-bus clock frequency
I2CClk
(I2CClkH + I2CClkL)
I
2
C-bus clock frequency
10 (minimum) 369 kHz
15 246 kHz
25 147 kHz
30 123 kHz
50 74 kHz
60 61 kHz
100 37 kHz
Table 9. I2CTO - I
2
C-bus time-out register (address 0x09h) bit description
Bit Symbol Description
7:1 TO[7:1] time-out value
0 TE enable/disable time-out function
logic 0 = disable
logic 1 = enable
time-out period
I2CTO 7:1256
57600
-----------------------------------------------
ondssec=
Table 10. I
2
C-bus status
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I
2
C-bus status description
11110000I2C_OK
1 1 1 1 0 0 0 1 I2C_NACK_ON_ADDRESS
11110010I2C_NACK_ON_DATA
11111000I2C_TIME_OUT
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 14 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
10. Limiting values
[1] This product includes circuitry specifically designed for the protection of its internal devices from the
damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be
taken to avoid applying greater than the rated maximum.
[2] Parameters are valid over operating temperature range unless otherwise specified. All voltages are with
respect to V
SS
unless otherwise noted.
[3] Based on package heat transfer, not device power consumption.
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1][2]
Symbol Parameter Conditions Min Max Unit
T
amb(bias)
bias ambient temperature 55 +125 C
T
stg
storage temperature 65 +150 C
V
I
input voltage referenced to V
SS
0.5 +5.5 V
I
OH(I/O)
HIGH-level output current
per input/output pin
GPIO3 to GPIO7 - 20 mA
all other pins - 8 mA
I
OL(I/O)
LOW-level output current
per input/output pin
-20mA
I
I/O(tot)(max)
maximum total I/O current - 120 mA
P
tot
/pack total power dissipation per package
[3]
-1.5W
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 15 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
11. Static characteristics
[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
[2] See Table 11 “
Limiting values” for steady state (non-transient) limits on I
OL
or I
OH
. If I
OL
/I
OH
exceeds the test condition, V
OL
/V
OH
may
exceed the related specification.
[3] Pin capacitance is characterized but not tested.
[4] Measured with GPIO in quasi-bidirectional mode.
[5] Measured with GPIO in high-impedance mode.
[6] GPIO in quasi-bidirectional mode with weak pull-up (applies to all GPIO pins with pull-ups). Does not apply to open-drain pins.
[7] GPIO pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when V
I
is approximately 2 V.
Table 12. Static characteristics
V
DD
= 2.4 V to 3.6 V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
I
DD
supply current V
DD
=3.6V
Operating mode; f = 7.3728 MHz - 9 15 mA
Idle mode; f = 7.3728 MHz - 3.25 5 mA
Power-down mode (sleep);
GPIO0 to GPIO7 as inputs;
inputs at V
DD
-5070A
V
POR
power-on reset voltage - - 0.2 V
V
th(HL)
negative-going threshold
voltage
except SCL, SDA 0.22V
DD
0.4V
DD
-V
V
IL
LOW-level input voltage SCL, SDA only 0.5 - 0.3V
DD
V
V
th(LH)
positive-going threshold
voltage
except SCL, SDA - 0.6V
DD
0.7V
DD
V
V
IH
HIGH-level input voltage SCL, SDA only 0.7V
DD
-5.5V
V
OL
LOW-level output
voltage
I
OL
=20mA
[2]
-0.61.0V
I
OL
=3.2mA
[2]
-0.20.3V
V
OH
HIGH-level output
voltage
I
OH
= 20 mA; Push-pull mode;
GPIO3 to GPIO7
0.8V
DD
--V
I
OH
= 3.2 mA; Push-pull mode;
GPIO0toGPIO2
V
DD
0.7 V
DD
0.4 - V
I
OH
= 20 mA; quasi-bidirectional
mode; all GPIOs
V
DD
0.3 V
DD
0.2 - V
C
io
input/output capacitance
[3]
- - 15 pF
I
IL
LOW-level input current logic 0; all ports; V
I
=0.4V
[4]
--80 A
I
LI
input leakage current all ports; V
I
=V
IL
or V
IH
[5]
--10 A
I
T(HL)
negative-going transition
current
logic 1-to-0; all ports; V
I
=2.0V at
V
DD
=3.6V
[6][7]
30 - 450 A
R
RESET_N(int)
internal pull-up
resistance on pin
RESET
10 - 30 k
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

SC18IM700IPW/S8HP

Mfr. #:
Buy SC18IM700IPW/S8HP
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC Master I2C-bus Controller w/UART
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet