SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 4 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
7. Functional description
The SC18IM700 is a bridge between a UART port and I
2
C-bus. The UART interface
consists of a full-functional advanced UART. The UART communicates with the host
through the TX and RX pins. The serial data format is fixed: one start bit, 8 data bits, and
one stop bit. After reset the baud rate defaults to 9600 bit/s, and can be changed through
the Baud Rate Generator (BRG) registers.
After a power-up sequence or a hardware reset, the SC18IM700 will send two continuous
bytes to the host to indicate a start-up condition. These two bytes are 0x4F and 0x4B;
‘OK’ in ASCII.
7.1 UART message format
The host initiates an I
2
C-bus data transfer, reads from and writes to SC18IM700 internal
registers through a series of ASCII commands. Table 4
lists the ASCII commands
supported by SC18IM700, and also their hexadecimal value representation.
Unrecognized commands are ignored by the device.
To prevent the host from handing the SC18IM700 due to an unfinished command
sequence, the SC18IM700 has a time-out feature. The delay between any two bytes of
data coming from the host should be less than 655 ms. If this condition is not met, the
SC18IM700 will time-out and clear the receive buffer. The SC18IM700 then starts to wait
for the next command from the host.
7.1.1 Write N bytes to slave device
The host issues the write command by sending an S character followed by an I
2
C-bus
slave device address, the total number of bytes to be sent, and I
2
C-bus data which begins
with the first byte (DATA 0) and ends with the last byte (DATA N). The frame is then
terminated with a P character. Once the host issues this command, the SC18IM700 will
access the I
2
C-bus slave device and start sending the I
2
C-bus data bytes.
Note that the second byte sent is the I
2
C-bus device slave address. The least significant
bit (W) of this byte must be set to 0 to indicate this is an I
2
C-bus write command.
Table 4. ASCII commands supported by SC18IM700
ASCII command Hex value Command function
S0x53I
2
C-bus START
P0x50I
2
C-bus STOP
R 0x52 read SC18IM700 internal register
W 0x57 write to SC18IM700 internal register
I 0x49 read GPIO port
O 0x4F write to GPIO port
Z 0x5A power down
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 5 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
7.1.2 Read N byte from slave device
The host issues the read command by sending an S character followed by an I
2
C-bus
slave device address, and the total number of bytes to be read from the addressed
I
2
C-bus slave. The frame is then terminated with a P character. Once the host issues this
command, the SC18IM700 will access the I
2
C-bus slave device, get the correct number of
bytes from the addressed I
2
C-bus slave, and then return the data to the host.
Note that the second byte sent is the I
2
C-bus device slave address. The least significant
bit (R) of this byte must be set to 1 to indicate this is an I
2
C-bus write command.
7.1.3 Write to 18IM internal register
The host issues the internal register write command by sending a W character followed by
the register and data pair. Each register to be written must be followed by the data byte.
The frame is then terminated with a P character.
Remark: Write and read from the internal 18IM register is processed immediately as soon
as the intended register is determined by 18IM.
Fig 3. Write N bytes to slave device
002aac048
NUMBER
OF BYTES
S CHAR.
SLAVE ADR.
+ W
host sends
DATA 0 DATA N P CHAR.
Fig 4. Read N byte from slave device
002aac049
NUMBER
OF BYTES
S CHAR.
SLAVE ADR.
+ R
host sends
18IM responds
P CHAR.
DATA 0 DATA N
Fig 5. Write to 18IM internal register
002aac050
W CHAR. REGISTER 0
DATA 0
REGISTER N DATA N P CHAR.
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 6 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
7.1.4 Read from 18IM internal register
The host issues the internal register read command by sending an R character followed
by the registers to be read. The frame is then terminated with a P character.
Once the command is issued, SC18IM700 will access its internal registers and returns the
contents of these registers to the host.
7.1.5 Write to GPIO port
The host issues the output port write command by sending an O character followed by the
data to be written to the output port. This command enables the host to quickly set any
GPIO pins programmed as output without having to write to the SC18IM700 internal
IOState register.
7.1.6 Read from GPIO port
The host issues the input port read command by sending an I character. This command
enables the host to quickly read any GPIO pins programmed as input without having to
read the SC18IM700 internal IOState register.
Once the command is issued, SC18IM700 will read its internal IOState register and
returns its content to the host.
7.1.7 Repeated START: read after write
The SC18IM700 also supports ‘read after write’ command as specified in the NXP
Semiconductors I
2
C-bus specification. This allows a read command to be sent after a
write command without having to issue a STOP condition between the two commands.
The host issues a write command as normal, then immediately issues a read command
without sending a STOP (P) character after the write command.
Fig 6. Read from 18IM internal register
002aac051
R CHAR. REGISTER 0 REGISTER N P CHAR.
18IM responds
DATA 0 DATA N
Fig 7. Write to output port
002aac052
O CHAR. DATA
P CHAR.
Fig 8. Read from output port
002aac053
I CHAR.
18IM responds
DATA
P CHAR.

SC18IM700IPW/S8HP

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC Master I2C-bus Controller w/UART
Lifecycle:
New from this manufacturer.
Delivery:
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