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SC18IM700IPW/S8HP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 16 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
12. Dynamic characteristics
Table 13. I
2
C-bus timing characteristics
All the timing limits are valid within the operating supply voltage and ambient temperature range; V
DD
= 2.4 V to 3.6 V;
T
amb
=
40
Cto+85
C; and refer to V
IL
and V
IH
with an input voltage of V
SS
to V
DD
.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode
I
2
C-bus
Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and START
condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START condition 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START condition 4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
HD;DAT
data hold time 0 - 0 - ns
t
VD;ACK
data valid acknowledge time - 0.6 - 0.6 s
t
VD;DAT
data valid time LOW-level - 0.6 - 0.6 s
HIGH-level - 0.6 - 0.6 s
t
SU;DAT
data set-up time 250 - 100 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
f
fall time of both SDA and SCL signals - 0.3 - 0.3 s
t
r
rise time of both SDA and SCL signals - 1 - 0.3 s
t
SP
pulse width of spikes that must be
suppressed by the input filter
-50-50ns
Fig 17. I
2
C-bus timing
SDA
SCL
002aab271
t
f
S
Sr
P S
t
HD;STA
t
LOW
t
r
t
SU;DAT
t
f
t
HD;DAT
t
HIGH
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
t
r
t
BUF
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 17 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
13. Package outline
Fig 18. Package outline SOT403-1 (TSSOP16)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153
99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
18
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
A
max.
1.1
pin 1 index
SC18IM700_3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 12 October 2017 18 of 24
NXP Semiconductors
SC18IM700
Master I
2
C-bus controller with UART interface
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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SC18IM700IPW/S8HP

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NXP Semiconductors
Description:
I/O Controller Interface IC Master I2C-bus Controller w/UART
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New from this manufacturer.
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