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SC18IS602BIPW/S8HP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 10 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
7.1.9 GPIO Read - Function ID F5h
The state of the pins defined as GPIO may be read into the SC18IS602B data buffer using
the GPIO Read function.
Note that this function does not return the value of the GPIO. To receive the GPIO
contents, a one-byte Read Buffer command would be required. The value of the Read
Buffer command will return the following byte.
Data for pins not defined as GPIO are undefined.
A GPIO Read is always performed to update the GPIO data in the buffer. The buffer is
undefined after the GPIO data is read back from the buffer. Therefore, reading data from
the GPIO always requires a two-message sequence (GPIO Read, followed by Read
Buffer).
7.1.10 GPIO Enable - Function ID F6h
At reset, the Slave Select pins (SS0, SS1, SS2 and SS3) are configured to be used as
slave select outputs. If these pins are not required for the SPI functions, they can be used
as GPIO after they are enabled as GPIO. Any combination of pins may be configured to
function as GPIO or Slave Selects.
After the GPIO Enable function is sent, the ports defined as GPIO will be configured as
quasi-bidirectional.
The data byte following the F6h command byte will determine which pins can be used as
GPIO. A logic 1 will enable the pin as a GPIO, while a logic 0 will disable GPIO control.
Fig 13. GPIO Read
Table 8. GPIO Read (F5h) bit allocation
7 6 5 4 3 2 1 0
XXXXSS3SS2SS1SS0
Fig 14. GPIO Enable
Table 9. GPIO Enable (F6h) bit allocation
7 6 5 4 3 2 1 0
XXXXSS3SS2SS1SS0
SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 11 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
7.1.11 GPIO Configuration - Function ID F7h
The pins defined as GPIO may be configured by software to one of four types on a
pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only.
Two bits select the output type for each port pin.
The SSn pins defined as GPIO, for example SS0.0 and SS0.1, may be configured by
software to one of four types. These are: quasi-bidirectional, push-pull, open-drain, and
input-only. Two configuration bits in GPIO Configuration register for each pin select the
type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression
circuit.
7.1.11.1 Quasi-bidirectional output configuration
Quasi-bidirectional outputs can be used both as an input and output without the need to
reconfigure the pin. This is possible because when the pin outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a large current. There are three pull-up
transistors in the quasi-bidirectional output that serve different purposes.
One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch
for the pin contains a logic 1. This very weak pull-up sources a very small current that will
pull the pin HIGH if it is left floating.
A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin
contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the
primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is
Table 10. GPIO Configuration (F7h) bit allocation
7 6 5 4 3 2 1 0
SS3.1 SS3.0 SS2.1 SS2.0 SS1.1 SS1.0 SS0.1 SS0.0
Table 11. GPIO Configuration (F7h) bit description
Bit Symbol Description
7 SS3.1 SS3[1:0] = 00: quasi-bidirectional
SS3[1:0] = 01: push-pull
SS3[1:0] = 10: input-only (high-impedance)
SS3[1:0] = 11: open-drain
6 SS3.0
5 SS2.1 SS2[1:0] = 00: quasi-bidirectional
SS2[1:0] = 01: push-pull
SS2[1:0] = 10: input-only (high-impedance)
SS2[1:0] = 11: open-drain
4 SS2.0
3 SS1.1 SS1[1:0] = 00: quasi-bidirectional
SS1[1:0] = 01: push-pull
SS1[1:0] = 10: input-only (high-impedance)
SS1[1:0] = 11: open-drain
2 SS1.0
1 SS0.1 SS0[1:0] = 00: quasi-bidirectional
SS0[1:0] = 01: push-pull
SS0[1:0] = 10: input-only (high-impedance)
SS0[1:0] = 11: open-drain
0 SS0.0
SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 12 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
pulled LOW by an external device, the weak pull-up turns off, and only the very weak
pull-up remains on. In order to pull the pin LOW under these conditions, the external
device has to sink enough current to overpower the weak pull-up and pull the pin below its
input threshold voltage.
The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up
LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a
logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks
quickly pulling the pin HIGH.
The quasi-bidirectional pin configuration is shown in Figure 15
.
Although the SC18IS602B is a 3 V device, most of the pins are 5 V tolerant. If 5 V is
applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from
the pin to V
DD
causing extra power consumption. Therefore, applying 5 V to pins
configured in quasi-bidirectional mode is discouraged.
A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression
circuit.
7.1.11.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a
pin configured in this manner must have an external pull-up, typically a resistor tied to
V
DD
. The pull-down for this mode is the same as for the quasi-bidirectional mode.
The open-drain pin configuration is shown in Figure 16
.
An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.
Fig 15. Quasi-bidirectional output configuration
002aac548
2 SYSTEM
CLOCK
CYCLES
weakstrong
very
weak
V
DD
PPP
V
SS
pin latch data
GPIO pin
glitch rejection
input data
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

SC18IS602BIPW/S8HP

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NXP Semiconductors
Description:
I/O Controller Interface IC I2C-bus to SPI Bridge SC18IS602B
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