SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 4 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration for TSSOP16
SC18IS602BIPW
SC18IS602BIPW/S8
SS0/GPIO0 A2
SS1/GPIO1 A1
RESET A0
V
SS
SS3/GPIO3
MISO V
DD
MOSI SPICLK
SDA SS2/GPIO2
SCL INT
002aac441
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 3. Pin description
Symbol Pin Type Description
SS0
/GPIO0 1 I/O SPI slave select output 0 (active LOW) or GPIO 0
SS1
/GPIO1 2 I/O SPI slave select output 1 (active LOW) or GPIO 1
RESET
3 I reset input (active LOW)
V
SS
4 - ground supply
MISO 5 I Master In, Slave Out
MOSI 6 O Master Out, Slave In
SDA 7 I/O I
2
C-bus data
SCL 8 I I
2
C-bus clock
INT
9 O Interrupt output (active LOW). This pin is an open-drain pin.
SS2
/GPIO2 10 I/O SPI slave select output 2 (active LOW) or GPIO 2
SPICLK 11 O SPI clock
V
DD
12 - supply voltage
SS3
/GPIO3 13 I/O SPI slave select output 3 (active LOW) or GPIO 3
A0 14 I address input 0
A1 15 I address input 1
A2 16 I address input 2
SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 5 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
7. Functional description
The SC18IS602B acts as a bridge between an I
2
C-bus and an SPI interface. It allows an
I
2
C-bus master device to communicate with any SPI-enabled device.
7.1 I
2
C-bus interface
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
2
C-bus may be used for test and diagnostic purposes
A typical I
2
C-bus configuration is shown in Figure 3. (Refer to NXP Semiconductors
UM10204, “I
2
C-bus specification and user manual”, at
www.nxp.com/documents/user_manual/UM10204.pdf
.)
The SC18IS602B device provides a byte-oriented I
2
C-bus interface that supports data
transfers up to 400 kHz. When the I
2
C-bus master is reading data from SC18IS602B, the
device will be a slave-transmitter. The SC18IS602B will be a slave-receiver when the
I
2
C-bus master is sending data. At no time does the SC18IS602B act as an I
2
C-bus
master, however, it does have the ability to hold the SCL line LOW between bytes to
complete its internal processes.
Fig 3. I
2
C-bus configuration
R
PU
002aac445
V
DD
SC18IS602B
I
2
C-BUS
DEVICE
I
2
C-BUS
DEVICE
I
2
C-bus
SDA
SCL
R
PU
SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 6 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
7.1.1 Addressing
The first seven bits of the first byte sent after a START condition defines the slave address
of the device being accessed on the bus. The eighth bit determines the direction of the
message. A ‘0’ in the least significant position of the first byte means that the master will
write information to a selected slave. A ‘1’ in this position means that the master will read
information from the slave. When an address is sent, each device in a system compares
the first seven bits after the START condition with its address. If they match, the device
considers itself addressed by the master as a slave-receiver or slave-transmitter,
depending on the R/W
bit.
A slave address of the SC18IS602B is comprised of a fixed and a programmable part.
The programmable part of the slave address enables the maximum possible number of
such devices to be connected to the I
2
C-bus. Since the SC18IS602B has three
programmable address bits (defined by the A2, A1, and A0 pins), it is possible to have
eight of these devices on the same bus.
The state of the A2, A1, and A0 pins are latched at reset. Changes made after reset will
not alter the address.
When SC18IS602B is busy after the address byte is transmitted, it will not acknowledge
its address.
7.1.2 Write to data buffer
All communications to or from the SC18IS602B occur through the data buffer. The data
buffer is 200 bytes deep. A message begins with the SC18IS602B address, followed by
the Function ID. Depending upon the Function ID, zero to 200 data bytes can follow.
The SC18IS602B will place the data received into a buffer and continue loading the buffer
until a STOP condition is received. After the STOP condition is detected, further
communications will not be acknowledged until the function designated by the Function ID
has been completed.
7.1.3 SPI read and write - Function ID 01h to 0Fh
Data in the buffer will be sent to the SPI port if the Function ID is 01h to 0Fh. The Function
ID contains the Slave Select (SS) to be used for the transmission on the SPI port. There
are four Slave Selects that can be used, with each SS being selected by one of the bits in
Fig 4. Slave address
R/W
002aac446
0 1 0 1 A2 A1 A0
fixed programmable
slave address
X
Fig 5. Write to data buffer
AS
002aac447
A P
FUNCTION ID
W
SLAVE ADDRESS 0 TO 200 BYTES
A

SC18IS602BIPW/S8HP

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC I2C-bus to SPI Bridge SC18IS602B
Lifecycle:
New from this manufacturer.
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