SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 7 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
the Function ID. There is no restriction on the number or combination of Slave Selects that
can be enabled for an SPI message. If more than one SSn
pin is enabled at one time, the
user should be aware of possible contention on the data outputs of the SPI slave devices.
The data on the SPI port will contain the same information as the I
2
C-bus data, but without
the slave address and Function ID. For example, if the message shown in Figure 6
is
transmitted on the I
2
C-bus, the SPI bus will send the message shown in Figure 7.
The SC18IS602B counts the number of data bytes sent to the I
2
C-bus port and will
automatically send this same number of bytes to the SPI bus. As the data is transmitted
from the MOSI pin, it is also read from the MISO pin and saved in the data buffer.
Therefore, the old data in the buffer is overwritten. The data in the buffer can then be read
back.
If the data from the SPI bus needs to be returned to the I
2
C-bus master, the process must
be completed by reading the data buffer. Section 8
gives an example of an SPI read.
7.1.4 Read from buffer
A read from the data buffer requires no Function ID. The slave address with the R/W bit
set to a ‘1’ will cause the SC18IS602B to send the buffer contents to the I
2
C-bus master.
The buffer contents are not modified during the read process.
A typical write and read from an SPI EEPROM is shown in Section 8.
Table 4. Function ID 01h to 0Fh
7 6 5 4 3 2 1 0
0000SS3SS2SS1SS0
Fig 6. I
2
C-bus message
Fig 7. SPI message
AS
002aac448
A P
FUNCTION
ID
WSLAVE ADDRESS
write to buffer
DATA 1
A A
DATA n
A
002aac451
SPI data
DATA 1
DATA n
Fig 8. Read from buffer
AS
002aac449
PR
SLAVE ADDRESS DATA 1
A A
DATA n
NA
SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 8 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
7.1.5 Configure SPI Interface - Function ID F0h
The SPI hardware operating mode, data direction, and frequency can be changed by
sending a ‘Configure SPI Interface’ command to the I
2
C-bus.
After the SC18IS602B address is transmitted on the bus, the Configure SPI Interface
Function ID (F0h) is sent followed by a byte which will define the SPI communications.
The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing
data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity. Figure 19
and
Figure 20
show the different settings of Clock Phase bit CPHA.
Fig 9. Configure SPI Interface
Table 5. Configure SPI Interface (F0h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol X X ORDER X MODE1 MODE0 F1 F0
Reset XX0X0000
Table 6. Configure SPI Interface (F0h) bit description
Bit Symbol Description
7:6 - reserved
5 ORDER When logic 0, the MSB of the data word is transmitted first.
If logic 1, the LSB of the data word is transmitted first.
4 - reserved
3:2 MODE1:MODE0 Mode selection
00 - SPICLK LOW when idle; data clocked in on leading edge
(CPOL = 0, CPHA = 0)
01 - SPICLK LOW when idle; data clocked in on trailing edge
(CPOL = 0, CPHA = 1)
10 - SPICLK HIGH when idle; data clocked in on trailing edge
(CPOL = 1, CPHA = 0)
11 - SPICLK HIGH when idle; data clocked in on leading edge
(CPOL = 1, CPHA = 1)
1:0 F1:F0 SPI clock rate
00 - 1843 kHz
01 - 461 kHz
10 - 115 kHz
11 - 58 kHz
SC18IS602B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 13 October 2017 9 of 26
NXP Semiconductors
SC18IS602B
I
2
C-bus to SPI bridge
7.1.6 Clear Interrupt - Function ID F1h
An interrupt is generated by the SC18IS602B after any SPI transmission has been
completed. This interrupt can be cleared (INT
pin HIGH) by sending a ‘Clear Interrupt’
command. It is not necessary to clear the interrupt; when polling the device, this function
may be ignored.
7.1.7 Idle mode - Function ID F2h
A low-power mode may be entered by sending the ‘Idle Mode’ command.
The Idle mode will be exited when its I
2
C-bus address is detected.
7.1.8 GPIO Write - Function ID F4h
The state of the pins defined as GPIO may be changed using the Port Write function.
The data byte following the F4h command will determine the state of SS3, SS2, SS1, and
SS0, if they are configured as GPIO. The Port Enable function will define if these pins are
used as SPI Slave Selects or if they are GPIO.
Fig 10. Clear Interrupt
AS
002aac452
PW
SLAVE ADDRESS F1h
A
Fig 11. Idle mode
AS
002aac453
PW
SLAVE ADDRESS F2h
A
Fig 12. GPIO Write
Table 7. GPIO Write (F0h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol X X X X SS3 SS2 SS1 SS0
Reset XXXX0000

SC18IS602BIPW/S8HP

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
I/O Controller Interface IC I2C-bus to SPI Bridge SC18IS602B
Lifecycle:
New from this manufacturer.
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