TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 25 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
Table 24. W2 - data write register bit allocation
7 6 5 4 3 2 1 0
MOD STD4 STD3 STD2 SB PLL GATE TRAP
Table 25. W2 - data write register bit description
Bit Symbol Description
7 MOD modulation
1 = negative; FM mono sound at ATV and dual mode
0 = positive; AM mono sound at ATV and dual mode
6 to 4 STD[4:2] vision IF; see
Table 26
3 SB sideband for sound IF and digital low IF
1 = upper
0=lower
2 PLL operating modes; see
Table 27
1 GATE PLL gating
1=on
0 = off
0 TRAP sound trap
1=on
0 = bypass
Table 26. Vision IF
Bit f
VIF
(MHz) Sideband
NYQOFF MOD STD4 STD3 STD2 TV1 = 0 (TSS) TV1 = 1 (QSS)
W7[0] W2[7] W2[6] W2[5] W2[4]
X 0 0 0 0 38.0 38.0 low
X 0 0 0 1 38.5 38.375 low
X 0 0 1 0 39.0 38.875 low
X 0 0 1 1 39.5 39.875 low
X 0 1 0 0 32.0 32.25 high
0 0 1 0 1 32.5 32.625 high
1 0 1 0 1 32.5 33.9 -
X 0 1 1 0 33.0 33.125 high
X 0 1 1 1 33.5 33.625 high
X 1 0 0 0 38.0 38.0 low
X 1 0 0 1 38.5 38.375 low
X 1 0 1 0 39.0 38.875 low
X 1 0 1 1 39.5 39.875 low
X 1 1 0 0 46.5 45.75 low
X 1 1 0 1 59.5 58.75 low
X 1 1 1 0 46.0 46.25 low
X 1 1 1 1 59.0 59.25 low
TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 26 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
Table 27. VIF PLL gating and detector mode
Bit Gating and detector mode
MOD PLL
W2[7] W2[2]
0 0 0 % gating in positive modulation mode (W2[1] = 1)
0 1 36 % gating in positive modulation mode (W2[1] = 1)
10π mode on; optimized for overmodulation in negative modulation mode;
f
PC
= 0 kHz ± 187.5 kHz
11π mode off; optimized for multipath in negative modulation mode;
f
PC
= 0 kHz ± 187.5 kHz
Table 28. W3 - data write register bit allocation
7 6 5 4 3 2 1 0
RESCAR AMUTE FMUTE FMWIDE0 DEEMT DEEM AGAIN1 AGAIN0
Table 29. W3 - data write register bit description
Bit Symbol Description
7 RESCAR video gain correction for residual carrier
1 = 20 % residual carrier
0 = 10 % residual carrier
6 AMUTE auto mute
1=on
0 = off
5 FMUTE forced mute
1=on
0 = off
4 FMWIDE0 FM window (W6[3] = 0)
1 = 475 kHz; normal FM phase detector steepness
0 = 237.5 kHz; high FM phase detector steepness
3 DEEMT de-emphasis time
1=50µs
0=75µs
2 DEEM de-emphasis
1=on
0 = off
1 and 0 AGAIN[1:0] audio gain
00=0dB
01 = 6dB
10 = 12 dB (only for FM mode)
11 = 18 dB (only for FM mode)
TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 27 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
Table 30. W4 - data write register bit allocation
7 6 5 4 3 2 1 0
VIFLEVEL BP MPP2S1 MPP2S0 AGCSW IFIN1 IFIN0 VIFIN
Table 31. W4 - data write register bit description
Bit Symbol Description
7 VIFLEVEL control of internal VIF mixer input level (W1[4] = 1) and
OUT1/OUT2 output level; see
Table 32
1 = reduced
0 = normal
6 BP SIF/DIF BP
1 = on (bit W6[0] = 0; see
Table 40)
0 = bypass
5 and 4 MPP2S[1:0] AGC or AFC output; see
Table 33
3 AGCSW VIF AGC switch state; see
Table 34
1 = VIF AGC hold (for diversity detection)
0 = VIF AGC external
2 and 1 IFIN[1:0] DIF/SIF input
00 = IF1A/B input
01 = IF3A/B input
10 = not used
11 = IF2A/B input
0 VIFIN VIF input
1 = IF1A/B input
0 = IF2A/B input

TDA9899HN/V2,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Up-Down Converters TDA9899HN/HVQFN48//V2/REEL 13 Q1 DP
Lifecycle:
New from this manufacturer.
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