TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 34 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
[1] Access to register W1 to W6 after selection of an easy setting mode would require a transfer of all W1 to W6 register data.
Table 46. Easy setting (to be used for fixed bit set-up only)
[1]
Bit Mode or
standard
Name Bit definition (hexadecimal)
EASY3 EASY2 EASY1 EASY0 W1 W2 W3 W4 W5 W6 W7
W8[3] W8[2] W8[1] W8[0]
0 0 0 0 off - -------
0 0 0 1 - - -------
0 0 1 0 - - -------
0 0 1 1 - - -------
0 1 0 0 - - -------
0 1 0 1 I 6.0 ES2 58 B1 CC 60 80 80 0C
0 1 1 0 B/G 5.5 ES3 38 B1 4C 60 40 80 0C
0 1 1 1 direct IF ES4 08 E1 64 62 00 81 08
1 0 0 0 M Japan 4.5 ES5 18 F1 44 73 00 80 08
1 0 0 1 LIF 6/36 ES6 28 88 60 61 AD 00 0C
1 0 1 0 - - -------
1 0 1 1 D/K 6.5 ES8 78 B1 4C 70 C0 80 0C
1 1 0 0 radio 5.5 ES9 BB B8 40 26 6B 00 04
1 1 0 1 - - -------
1 1 1 0 L 6.5 ES11 79 33 00 60 C0 C0 0C
1 1 1 1 - - -------
Table 47. W9 - data write register bit allocation
7 6 5 4 3 2 1 0
DAGCSLOPE TAGCIS TAGCTC TOPNEG4 TOPNEG3 TOPNEG2 TOPNEG1 TOPNEG0
Table 48. W9 - data write register bit description
Bit Symbol Description
7 DAGCSLOPE AGCDIN input characteristic; see
Figure 46
1 = high voltage for high gain
0 = low voltage for high gain
6 TAGCIS tuner AGC IF input
1 = inverse to VIF input
0 = aligned to VIF input
5 TAGCTC tuner AGC time constant
1 = 2nd mode
0 = normal
4 to 0 TOPNEG[4:0] TOP adjustment for integral loop mode; see
Table 49
TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 35 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
[1] See Table 55 for parameter tuner takeover point accuracy (α
acc(set)TOP
).
[1] See Table 55 for parameter tuner takeover point accuracy (α
acc(set)TOP2
).
Table 49. Tuner takeover point adjustment bits W9[4:0]
Bit TOP adjustment (dBµV)
TOPNEG4 TOPNEG3 TOPNEG2 TOPNEG1 TOPNEG0
W9[4] W9[3] W9[2] W9[1] W9[0]
1111198.2 typical
:::::see
Figure 12
1000078.7
[1]
:::::seeFigure 12
0000057.9 typical
Table 50. W10 - data write register bit allocation
7 6 5 4 3 2 1 0
0 0 XPOTPOS TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0
Table 51. W10 - data write register bit description
Bit Symbol Description
7 and 6 - 0 = fixed value
5 XPOTPOS TOP derived from IF AGC via I
2
C-bus or potentiometer
1 = TOP adjustment by external potentiometer at pin TOP2
0 = see
Table 52
4 to 0 TOPPOS[4:0] TOP adjustment for TAGC derived from IF AGC; see
Table 52
Table 52. Tuner takeover point adjustment bits W10[4:0]
Bit TOP adjustment (dBµV)
TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0
W10[4] W10[3] W10[2] W10[1] W10[0]
1111199 typical
:::::see
Figure 12
1000081
[1]
:::::seeFigure 12
0000061 typical
TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 36 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
10. Limiting values
[1] Class 2 according to JESD22-A114.
[2] Class B according to EIA/JESD22-A115.
11. Thermal characteristics
12. Characteristics
12.1 Analog TV signal processing
Table 53. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
P
supply voltage - 5.5 V
V
n
voltage on any other pin all pins except ground 0 V
P
V
t
sc
short-circuit time to ground or V
P
-10 s
T
stg
storage temperature 40 +150 °C
T
amb
ambient temperature 20 +70 °C
T
case
case temperature TDA9899HL (LQFP48) - 105 °C
TDA9899HN (HVQFN48) - 115 °C
V
esd
electrostatic discharge voltage human body model
[1]
- ±3000 V
machine model
[2]
- ±300 V
Table 54. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction
to ambient
in free air; 2 layer board
TDA9899HL (LQFP48) 67 K/W
TDA9899HN (HVQFN48) 48 K/W
R
th(j-c)
thermal resistance from junction
to case
TDA9899HL (LQFP48) 19 K/W
TDA9899HN (HVQFN48) 10 K/W
Table 55. Characteristics
V
P
=5V; T
amb
=25
°
C; see Table 26 for input frequencies; B/G standard is used for the specification (f
PC
= 38.375 MHz;
f
SC
= 32.875 MHz; PC / SC = 13 dB; f
AF
= 400 Hz); input level V
i(IF)
= 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50
via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of
Figure 49; unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply; pin V
P
V
P
supply voltage
[1]
4.5 5.0 5.5 V
I
P
supply current - - 190 mA

TDA9899HN/V2,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Up-Down Converters TDA9899HN/HVQFN48//V2/REEL 13 Q1 DP
Lifecycle:
New from this manufacturer.
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