TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 28 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
[1] Intercarrier output level based on wide-band AGC of SIF amplifier.
[2] SIF output level based on wide-band AGC of SIF amplifier.
[3] Intercarrier output level based on narrow-band AGC of FM amplifier.
Table 32. List of output signals at OUT1 and OUT2
Bit Output signal at
TV2 TV1 DIRECT FM EXTFIL OUT1A, OUT1B OUT2A, OUT2B
W1[4] W1[3] W6[0] W1[1] W1[0]
0 0 0 X X zero IF I zero IF Q
0 1 0 X X low IF off
0 X 1 X X off direct IF
1 X 1 0 0 intercarrier
[1]
SIF
[2]
1 X 1 0 1 intercarrier
[3]
SIF
[2]
1 X 1 1 0 intercarrier
[3]
SIF
[2]
1 X 1 1 1 intercarrier
[1]
SIF
[2]
1 X 0 0 0 intercarrier
[1]
off
1 X 0 0 1 intercarrier
[3]
off
1 X 0 1 0 intercarrier
[3]
off
1 X 0 1 1 intercarrier
[1]
off
Table 33. Output mode at pin MPP2 for ATV; dual or radio mode
Bit Pin MPP2 output mode
WAFP RADIO MPP2S1 MPP2S0
W7[6] W1[7] W4[5] W4[4]
0 X 0 0 gain control voltage of FM PLL
0 X 0 1 gain control voltage of SIF amplifier
0 X 1 0 TAGC monitor voltage
0011AFC current output, VIF PLL
0111AFC current output, radio mode
1 X 0 0 voltage output of weak audio signal detector
Table 34. Control function of bit AGCSW
W4[3]
(AGCSW)
V
AGCSWI
Function
0 < 1 V VIF AGC from internal
0 > 2 V VIF AGC from pin AGCVIN
1 < 1 V VIF AGC is not on hold
1 > 2 V VIF AGC is on hold
TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 29 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
[1] For bit description of TV1 and TV2 see Table 16 W1[3] and W1[4] and Table 17.
Table 35. W5 - data write register bit allocation
7 6 5 4 3 2 1 0
FSFREQ1 FSFREQ0 SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0
Table 36. W5 - data write register bit description
[1]
Bit Symbol Description
7 and 6 FSFREQ[1:0] DTV filter or sound trap selection for video
ATV; sound trap; TV2 = 1
00 = M/N standard (4.5 MHz)
01 = B/G standard (5.5 MHz)
10 = I standard (6.0 MHz)
11 = D/K and L/L-accent standard (6.5 MHz)
DTV (zero IF); low-pass cut-off frequency; TV2 = 0 and TV1 = 0
00 = 3.0 MHz
01 = 3.5 MHz
10 = 4.0 MHz
11 = not used
DTV (low IF); upper BP cut-off frequency; TV2 = 0 and TV1 = 1
00 = 7.0 MHz
01 = 8.0 MHz
10 = 9.0 MHz
11 = not used
5 to 0 SFREQ[5:0] synthesizer frequencies; see
Table 37 and Table 38
TDA9899_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 15 January 2008 30 of 103
NXP Semiconductors
TDA9899
Multistandard hybrid IF processing including car mobile
Table 37. DIF/SIF synthesizer frequencies (using bit TWOFLO = 0)
Bit f
synth
(MHz)
SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0
W5[5] W5[4] W5[3] W5[2] W5[1] W5[0]
11111122.0
11111022.5
11110123.0
11110023.5
11101124.0
11101024.5
11100125.0
11100025.5
11011126.0
11011026.5
11010127.0
11010027.5
11001128.0
11001028.5
11000129.0
11000029.5
10111130.0
10111030.5
10110131.0
10110031.5
10101132.0
10101032.5
10100133.0
10100033.5
10011134.0
10011034.5
10010135.0
10010035.5
10001136.0
10001036.5
10000137.0
10000037.5
01111138.0
01111038.5
01110139.0
01110039.5
01101140.0
01101040.5
01100141.0

TDA9899HN/V2,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Up-Down Converters TDA9899HN/HVQFN48//V2/REEL 13 Q1 DP
Lifecycle:
New from this manufacturer.
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