Features
Smart Card Interface
Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards
Card Clock Stop High or Low for Card Power-down Modes
Support Synchronous Cards with C4 and C8 Contacts
Card Detection and Automatic de-activation Sequence
Programmable Activation Sequence
Direct Connection to the Smart Card
Logic Level Shifters
Short Circuit Current Limitation (see electrical characteristics)
8kV+ ESD Protection (MIL/STD 883 Class 3)
Programmable Voltage
5V ±5% at 65 mA (Class A)
3V ±0.2V at 65 mA (Class B)
1.8V ±0.14V at 40 mA
Low Ripple Noise: < 200 mV
Versatile Host Interface
ICAM (Conditional Access) Compatible
Two Wire Interface (TWI) Link
Programmable Address Allow up to 8 Devices
Programmable Interrupt Output
Automatic Level Shifter (1.6V to V
CC
)
Reset Output Includes
Power-On Reset (POR)
Power-Fail Detector (PFD)
High-efficiency Step-up Converter: 80 to 98% Efficiency
Extended Voltage Operation: 3V to 5.5V
Low Power Consumption
180 mA Maximum In-rush Current
30 µA Typical Power-down Current (without Smart Card)
4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24B)
18 to 48MHz Clock input (for AT83C24NDS)
Industrial Temperature Range: -40 to +85°C
Packages: SO28 and QFN28
Description
The AT83C24B is a smart card reader interface IC for smart card reader/writer appli-
cations such as EFT/POS terminals and set top boxes. It enables the management of
any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in
parallel using the programmable TWI address.
Its high efficiency DC/DC converter, low quiescent current in standby mode makes it
particularly suited to low power and portable applications. The reduced bill of material
allows reducing significantly the system cost. A sophisticated protection system guar-
antees timely and controlled shutdown upon error conditions.
The AT83C24NDS is a dedicated version approved by NDS for use with NDS Video-
Guard conditional access software in set-top boxes. All AT83C24B datasheet is
applicable to AT83C24BNDS. The main differences between AT83C24B and
AT83C24NDS are listed below:
1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS,
CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24B
2/ 18MHz minimum on input clock for AT83C24NDS
3/ Up to 10µF for capacitor connected on CVCC pin for AT83C24B,
3.3µF mandatory for AT83C24NDS
Smart Card
Reader
Interface with
Power
Management
AT83C24B
AT83C24NDS
4234G–SCR–01/07
2
4234G–SCR–01/07
AT83C24
Acronyms
TWI: Two-wire Interface
POR: Power On Reset
PFD: Power Fail Detect
ART: Automatic Reset Transition
ATR: Answer To Reset
MSB: Most Significant Bit
LSB: Least Significant bit
SCIB: Smart Card Interface Bus
Block Diagram
PRES/ INT
CLK
VSS
CRST
CPRES
CIO, CC4, CC8
CCLK
CVCC
LI
RESET
Voltage
supervisor
POR/PFD
TWI
Controller
Clocks Controller
DC/DC
Converter
Analog
Drivers
SCL
SDA
I/O, C4, C8
DVCC
EVCC
A2/CK, A1/RST, A0/3V, CMDVCC
Timer
16 Bits
Main
Control
& Logic Unit
CVSS
CVCCIN
VCC
3
4234G–SCR–01/07
AT83C24
Pin Description
Pinouts (Top View)
28-pin SOIC Pinout QFN28 pinout
Note: 1. NC = Not Connected
2. SOIC and QFN packages are available for
AT83C24B and for AT83C24NDS
Signals
A1
A2
A0
1
EVCC
CCLK
CRST
SCL
VCC
RESET
CVSS
CVCCin
I/O
CLK
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
LI
PRES/INT
DVCC
VSS
SDA
CPRES
12
18
17
11
C8
CIO
C4
16
15
CC8
CMDVCC
CC4
1
VSS
V
CC
CVSS
LI
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
17
18
19
20
21
22
23
24
25
26
27
28
TOP VIEW
QFN 28
CIO
CC8
CVCCin
CRST
CPRES
CC4
CCLK
CMDVCC
RESET
DVCC
C8
CLK
PRES/INT
C4
/CK
/CK
/RST
A0
/RST
/3V
/3V
CVCC
CVCC
SDA
SCL
A1
A2
I/O
EVCC
13
14
NC
NC
NC
NC
Table 1. Ports Description
Pad Name Pad Internal
Power Supply
ESD
Limits
Pad
Type Description
A2/CK-
A1/RST-
A0/3V
EVCC 3 kV I
Microcontroller Interface Function:
TWI bus slave address selection input.
A2/CK and A1/RST pins are respectively connected to CCLK and CRST signals in
“transparent mode” (see page 19 ).
A0/3V is used for hardware activation to select CVCC voltage (3V or 5V).
The slave address of the device is based on the value present on A2, A1, A0 on the
rising edge of RESET pin (see Table 2). In fact, the address is taken internally at the 11th
CLK rising edge.
PRES/INT EVCC
3 kV
O
open-
drain
Microcontroller Interface Function:
Depending on IT_SEL value (see CONFIG4 register),
PRES/INT outputs card presence status or interruptions (page 9)
An internal Pull-up (typ 330kΩ,see Table 18)to EVCC can be activated in the pad if
necessary using INT_PULLUP bit (CONFIG4 register).
Remark: during power up and before registers configuration, the PRES/INT signal must
be ignored.
RESET VCC
3 kV
I/O
open-
drain
Microcontroller Interface Function:
Power-on reset
A low level on this pin keeps the AT83C24 under reset even if applied on power-on.
It also resets the AT83C24 if applied when the AT83C24 is running (see Power
monitoring §).
Asserting RESET when the chip is in Shut-down mode returns the chip to normal
operation.
AT83C24 is driving the Reset pin Low on power-on-reset or if power fail on V
CC
or
DVCC (see POWERMON bit in CONFIG4 register), this can be used to reset or
interrupt other devices. After reset, AT83C24 needs to be reconfigured before
starting a new card session.

AT83C24B-PRRUL

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
Interface - Specialized 3V Smart card reader
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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