15
4234G–SCR–01/07
AT83C24
Software Activation (DC/DC Started With Writing in VCARD[1:0] bits) and ART bit = 1
Initial conditions: CARDRST bit = 0, CKSTOP bit =1, IODIS bit = 1.
The following sequence can be applied:
1. Card Voltage is set by software to the required value (VCARD[1:0] bits in CONFIG0
register). This writing starts the DC/DC.
2. Wait the end of the DC/DC init with a polling on VCARDOK bit (STATUS register) or
wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in CONFIG4 register).
When VCARDOK bit is set (by hardware), CARDIO bit should be set by software.
3. CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have the
clock running. IODIS is reset to drive the I/O, C4, C8 pins and the CIO,CC4, CC8
pins according to each other.
4. CARDRST bit (see INTERFACE register) is set by software.
Automatic Reset Transition description:
A 16-bit counter starts when CARDRST bit is set. It counts card clock cycles. The CRST signal
is set when the counter reaches the TIMER[1-0] value which corresponds to the “tb” time (Figure
11).The counter is reseted when the CRST pin is released and it is stopped at the first start bit of
the Answer To Request (ATR) on CIO pin.
The CIO pin is not checked during the first 200 clock cycles (ta on Figure 11). If the ATR arrives
before the counter reaches Timer[1-0] value, the activation sequence fails, the CRST signal is
not set and the Capture[1-0] register contains the value of the counter at the arrival of the ATR.
If the ATR arrives after the rising edge on CRST pin and before the card clock counter overflows
(65535 clock cycles), the activation sequence completes. The Capture[1-0] register contains the
value of the counter at the arrival of the ATR (tc time on Figure 11).
Figure 11. Software activation with ART bit = 1
CVCC
CRST
CCLK
tc
tb
ta
CIO
CARDRST bit set
1
2
3
4
