9
4234G–SCR–01/07
AT83C24
Read Command
After the slave address has been configured, the read command allows to read one or several
bytes in the following order:
• STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1, TIMER0,
CAPTURE1, CAPTURE0
• FFh is completing the transfer if the microcontroller attempts to read beyond the last byte.
Note: Flags are only reset after the corresponding byte read has been acknowledged by the master.
Table 4. Read Command Description
Interrupts
The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register).
• If IT_SEL= 0, the PRES/INT output is High by default (on chip pull up or open drain).
PRES/INT is driven Low by any of the following event:
– INSERT bit set in CONFIG0 register (card insertion/extraction or bit set by software )
– VCARD_INT bit set in STATUS register (the DC/DC output voltage has settled)
– over-current detection on CVCC
– VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by
software)
– ATRERR bit set in CONFIG0 register (no ATR before the card clock counter
overflows or bit set by software).This control of ATR timing is only available if ART bit
=1.
If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will release
PRES/INT pin to high level.
Several AT83C24 devices can share the same interrupt and the microcontroller can identify
the interrupt sources by polling the status of the AT83C24 devices using TWI commands.
• If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with existing
devices) the PRES/INT output is High to indicate a card is present and none of the following
event has occured:
Byte Description Byte Value
Address byte 0100 A
2
A
1
A
0
1
Data byte 1 STATUS
Data byte 2 CONFIG0
Data byte 3 CONFIG1
Data byte 4 CONFIG2
Data byte 5 CONFIG3
Data byte 6 CONFIG4
Data byte 7 INTERFACE
Data byte 8 TIMER 1 (MSB)
Data byte 9 TIMER 0 (LSB)
Data byte 10 CAPTURE 1 (MSB)
Data byte 11 CAPTURE 0 (LSB)
Data byte 12 0xFF
