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AT83C24B-PRRUL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
25
4234G–SCR–01/07
AT83C24
Table 10. CONFIG4 (Config Byte 4)
7 6 5 4 3 2 1 0
X X X STEPREG INT_PULLUP POWERMON IT_SEL CRST_SEL
Bit Number Bit Mnemonic Description
7-5 X-X-X These bits should not be set.
4 STEPREG
Step Regulator mode
Clear this bit to enable the automatic step-up converter (CVCC is stable even if VCC is not higher than CVCC).
Set this bit to permanently disable the step-up converter (CVCC is stable only if VCC is sufficiently higher than
CVCC).
This bit must be set before activating the DC/DC converter if no external coil is present.
The reset value is 0.
This bit must always be set if no external coil is used
3 INT_PULLUP
Internal pull-up
Set this bit to activate the internal pull-up (connected internally to EVCC) on PRES/INT pin.
Clear this bit to deactivate the internal pull-up.
PRES/INT is an open drain output with a programmable internal pull up.
The reset value is 0.
2 POWERMON
Power monitor
Set this bit to monitor any glitch on the Digital Supply Voltage (DVCC) of the AT83C24.
Clear this bit to monitor any glitch on VCC.
The reset value is 0.
1 IT_SEL
Interrupt Select
Set this bit to disable INSERT and VCARD_INT interrupts. Then PRES/INT is pulled up when a card is present
and no error is detected.
Clear this bit to have all the interrupt sources enabled and active Low.
IT_SEL must be set to enable a hardware activation with CMDVCC.
The reset value is 0.
0 CRST_SEL
Card Reset Selection
Set this bit to have the CRST pin driven by hardware through the A1 pin (only with hardware activation).
Clear this bit to have the CRST pin driven by software through the CARDRST bit.
CRST_SEL must be set when CMDVCC is used (hardware activation).
The reset value is 0.
26
4234G–SCR–01/07
AT83C24
Table 11. INTERFACE (Interface Byte)
7 6 5 4 3 2 1 0
0 IODIS CKSTOP CARDRST CARDC8 CARDC4 CARDCK CARDIO
Bit Number Bit Mnemonic Description
7 0 This bit should not be set.
6 IODIS
Card I/O isolation
Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 respectively and to put
I/O, C4, C8 in Hi-Z. This can be used to have the I/O, and C4 and C8 pins of the host communicating with
another AT83C24 interface, while CIO, CC4 and CC8 are driven by software (or if the card is in standby or
power-down modes).
Clear this bit to drive the I/O/CIO, C4/CC4 and C8/CC8 pins according to each other. This can be used to activate
asynchronous cards.
The reset value is 1.
5 CKSTOP
CARD Clock Stop
Set this bit to stop CCLK according to CARDCK. This can be used to set asynchronous cards in power-down
mode (GSM) or to drive CCLK by software.
Clear this bit to have CCLK running according to CKS. This can be used to activate asynchronous cards.
Note: 1. When this bit is changed a special logic ensures that no glitch occurs on the CCLK pin
and actual configuration changes can be delayed by half a period to two periods of
CCLK.
2. CKSTOP must be set before switching on the DC/DC with VCARD[1:0].
The reset value is 1.
4 CARDRST
Card Reset
Set this bit to enter a reset sequence according to ART bit value.
Clear this bit to drive a low level on the CRST pin.
The reset value is 0.
3 CARDC8
Card C8
Set this bit to drive the CC8 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CC8 pin (according to IODIS bit value).
The reset value is 0.
2 CARDC4
Card C4
Set this bit to drive the CC4 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CC4 pin (according to IODIS bit value).
The reset value is 0.
1 CARDCK
Card Clock
Set this bit to set a high level on the CCLK pin (according to CKSTOP bit value).
Clear this bit to drive a low level on the CCLK pin.
The reset value is 0.
0 CARDIO
Card I/O
Set this bit to drive the CIO pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CIO pin (according to IODIS bit value).
The reset value is 0.
27
4234G–SCR–01/07
AT83C24
Reset value = 0x00000001
Table 12. STATUS (Status Byte)
7 6 5 4 3 2 1 0
CC8 CC4 CARDIN VCARDOK X VCARD_INT CRST CIO
Bit Number Bit Mnemonic Description
7 CC8
Card CC8
This bit provides the actual level on the CC8 pin when read.
The reset value is 0.
6 CC4
Card CC4
This bit provides the actual level on the CC4 pin when read.
The reset value is 0.
5 CARDIN
Card Presence Status
This bit is set when a card is detected.
It is cleared otherwise.
4 VCARD_OK
Card Voltage Status
This bit is set by the DCDC when the output voltage remains within the
voltage range specified by VCARD[1:0] bits.
It is cleared otherwise.
The reset value is 0.
3 X This bit should not be set.
2 VCARD_INT
Card voltage interrupt
This bit is set when VCARD_OK bit is set.
This bit is cleared when read by the microcontroller.
The reset value is 0.
1 CRST
Card RST
This bit provides the actual level on the CRST pin when read.
The reset value is 0.
0 CIO
Card I/O
This bit provides the actual level on the CIO pin when read.
The reset value is 0.
Table 13. TIMER 1 (Timer MSB)
7 6 5 4 3 2 1 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit
Number
Bit
Mnemonic Description
7 - 0 Bits 15 - 8 Timer MSB (bits 15 to 8)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

AT83C24B-PRRUL

Mfr. #:
Buy AT83C24B-PRRUL
Manufacturer:
Microchip Technology / Atmel
Description:
Interface - Specialized 3V Smart card reader
Lifecycle:
New from this manufacturer.
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