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MAX1494CCJ+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
22 ______________________________________________________________________________________
START: Start Bit. The first 1 clocked into the
MAX1492/MAX1494 is the first bit of the
command byte.
(R/W): Read/Write. Set this bit to 1 to read from
the specified register. Set this bit to 0 to
write to the selected register. Note that
certain registers are read-only. Write com-
mands to a read-only register are
ignored.
(RS4–RS0): Register Address Bits. RS4 to RS0 specify
which register is accessed.
X: Don’t care.
MSB LSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
START (1) R/W RS4 RS3 RS2 RS1 RS0 X
This register contains the status of the conversion
results.
SIGN: Latched Negative-Polarity Indicator.
Latches high when the result is negative.
Clears by reading the status register,
unless the condition remains true.
OVER: Overrange Bit. Latches high if an over-
range condition occurs (the ADC result is
larger than the value in the overrange reg-
ister). Clears by reading the status regis-
ter, unless the condition remains true.
UNDER: Underrange Bit. Latches high if an under-
range condition occurs (the ADC result is
less than the value in the underrange regis-
ter). Clears by reading the status register,
unless the condition remains true.
LOW_BATT: Low-Battery Bit. Latches high if the voltage
at the LOWBATT is lower than 2.048V (typ).
Clears by reading the status register,
unless the condition remains true.
DRDY: Data-Ready Bit. Latches high to indicate
a completed conversion result with valid
data. Read the ADC Result-Register 1 to
clear this bit.
MSB LSB
SIGN OVER UNDER LOW_BATT DRDY 0 0 0
This register is the primary control register for the
MAX1492/MAX1494. It is a 16-bit read/write register. It
is used to indicate the desired clock and reference
source. It sets the LCD controls, range modes, power-
down modes, offset calibration, and the reset register
function (CLR).
MSB
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
SPI/ADC EXTCLK INTREF DP_EN DPSET2 DPSET1 PD_DIG PD_ANA
LSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HOLD PEAK RANGE CLR SEG_SEL OFFSET_CAL1 OFFSET_CAL2 0
Status Register (Read Only):
Control Register (Read/Write):
Command Byte (Write Only):
Default values: 0000h
Default values: 00h
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
______________________________________________________________________________________ 23
SPI/ADC: (Default = 0) Display Select Bit. The
SPI/ADC bit controls selection of the
data fed into the LCD data register. A
1 in this location selects SPI/QSPI/
MICROWIRE data (the user writes this
data to the LCD data register). A 0 in
this location selects the ADC result
register data, unless hold or peak
functions are active (Table 6).
EXTCLK: (Default = 0) External Clock Select
Bit. The EXTCLK bit controls selec-
tion of the internal clock or an exter-
nal clock source. A 1 in this location
selects the signal at the CLK input as
the clock source. A 0 in this location
selects the internal clock oscillator.
Toggle the PD_DIG and PD_ANA
after changing the EXTCLK bit.
INTREF: (Default = 0) Reference Select Bit. For
internal reference operation, set
INTREF to 1. For external reference
operation, set INTREF to 0.
DP_EN: (Default = 0) Decimal-Point Enable
Bit (Tables 2 and 3).
DPSET[2:1]: (Default = 00) Decimal-Point
Selection Bits (Tables 2 and 3).
HOLD: (Default = 0) Hold Bit. When set to 1,
the LCD register does not update
from the ADC conversion results and
holds the last result on the LCD. The
MAX1492/MAX1494 continue to per-
form conversions during HOLD
(Table 6).
PEAK: (Default = 0) Peak Bit. When set to 1
(and the HOLD bit is set to 0), the
LCD shows the result stored in the
peak register (Table 6).
PD_ANA: (Default = 0) Power-Down Analog
Select Bit. When set to 1, the analog
circuits (analog modulator and ADC
input buffers) go into the power-down
mode. When set to 0, the device is in
full power-up mode.
PD_DIG: (Default = 0) Power-Down Digital
Select Bit. When set to 1, the digital
circuits (digital filter and LCD drivers)
go into power-down mode. This also
resets the values of the internal
SRAM (in the digital filter) to zeros.
When set to 0, the device returns to
full power-up mode.
RANGE: (Default = 0) Input-Range Select Bit.
When set to 0, the input voltage
range is ±2V. When set to 1, the input
voltage range is ±200mV. Toggle the
PD_DIG and PD_ANA after changing
the RANGE bit.
CLR: (Default = 0) Clear-All-Registers Bit.
When set to 1, all the registers reset
to their power-on reset states when
CS makes a low-to-high transition.
SEG_SEL: (Default = 0) LCD Segment-Selection
Bit. When set to 1, the LCD segment
drivers use the LCD segment regis-
ters to display individual segments
that can form letters or numbers or
other information on the display. The
LCD data register is NOT displayed.
Send the data first to the LCD seg-
ment-display registers and then set
this bit high (Table 6).
OFFSET_CAL1: (Default = 0) Automatic-Offset Enable
Bit. When set to 1, the MAX1492/
MAX1494 disable automatic offset cali-
bration. When this bit is set to 0, auto-
matic offset calibration is enabled.
OFFSET_CAL2: (Default = 0) Enhanced Offset-
Calibration Start Bit (MAX1494 Only
and RANGE = 1). To achieve the low-
est possible offset in the ±200mV
input range, perform an enhanced
offset calibration by setting this bit to
1. The calibration takes approximate-
ly 9 cycles (1800ms). After the cali-
bration completes, set this bit to 0 to
resume ADC conversions.
Note: When changing any one of the following control
bits: OFFSET_CAL1, RANGE, PD_ANA, PD_DIG,
INTREF, and EXTCLK, wait 800ms before reading the
ADC results.
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
24 ______________________________________________________________________________________
Default values: 7CF0h (for MAX1492, +1999)
4E1Fh (for MAX1494, +19,999)
The overrange register is a 16-bit read/write register
(D15 is the MSB). When the conversion result exceeds
the value in the overrange register, the OVER bit in the
status register latches to 1. The LCD shows a 1 fol-
lowed by 4 dashes for the MAX1494 or a 1 followed by
3 dashes for the MAX1492 (Table 4).
The data is represented in two’s complement format.
SEG_SEL SPI/ADC HOLD PEAK DISPLAYS VALUES FROM
1 X X X LCD Segment Registers
0 1 X X LCD Display Register (User Written)
0 0 1 X LCD Display Register
0 0 0 1 Peak Register
0 0 0 0 ADC Result Register
Table 6. LCD Priority Table
X = Don’t care.
Underrange Register (Read/Write):
Overrange Register (Read/Write):
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Default values: 8300h (for MAX1492, -2000)
B1E0h (for MAX1494, -20,000)
The underrange data register is 16-bit read/write regis-
ter (D15 is the MSB). When the conversion result falls
below the value in the underrange register, the UNDR
bit in the status register sets to 1. The LCD shows a -1
followed by 4 dashes for the MAX1494 or a -1 followed
by 3 dashes for the MAX1492 (Table 4).
The data is represented in two’s complement format.
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Default values: 0000h
The LCD segment-display register 1 is a 16-bit
read/write register. When the SEG_SEL bit (in the con-
trol register) is set to 1, the MAX1492/MAX1494 provide
direct access to individual LCD segments. The bits in
the LCD segment-display register determine if a seg-
ment is on or off. Write a 0 to this register to turn on a
segment and a 1 to turn off a segment.
MSB LSB
A2 G2 D2 F2 E2 DP2 ANN B1 C1 A1 G1 D1 F1 E1 DP1 0
LCD Segment-Display Register 1 (Read/Write):
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

MAX1494CCJ+

Mfr. #:
Buy MAX1494CCJ+
Manufacturer:
Maxim Integrated
Description:
LCD Drivers 4.5 Digit ADC w/LCD Drivers
Lifecycle:
New from this manufacturer.
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