©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
13
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A
23
-A
0
]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T
BP
for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
Figure 7: Byte-Program Sequence
1417 ByteProg.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD. D
IN
02
HIGH IMPEDANCE
15 16
23
24
31
32
39
MODE 0
MODE 3
MSBMSB
MSB
LSB
©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
14
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the
next sequential address location. This feature decreases total programming time when multiple bytes
or entire memory array is to be programmed. An AAI Word program instruction pointing to a protected
memory area will be ignored. The selected address range must be in the erased state (FFH) when ini-
tiating an AAI Word Program operation. While within AAI Word Programming sequence, only the fol-
lowing instructions are valid: for software end-of-write detection—AAI Word (ADH), WRDI (04H), and
RDSR (05H); for hardware end-of-write detection—AAI Word (ADH) and WRDI (04H). There are three
options to determine the completion of each AAI Word program cycle: hardware detection by reading
the Serial Output, software detection by polling the BUSY bit in the software status register, or wait T
BP.
Refer to“End-of-Write Detection” for details.
Prior to any write operation, the Write-Enable (WREN) instruction must be executed. Initiate the AAI
Word Program instruction by executing an 8-bit command, ADH, followed by address bits [A
23
-A
0
]. Fol-
lowing the addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB (Bit
0). The first byte of data (D0) is programmed into the initial address [A
23
-A
1
] with A
0
=0, the second
byte of Data (D1) is programmed into the initial address [A
23
-A
1
] with A
0
=1. CE# must be driven high
before executing the AAI Word Program instruction. Check the BUSY status before entering the next
valid command. Once the device indicates it is no longer busy, data for the next two sequential
addresses may be programmed, followed by the next two, and so on.
When programming the last desired word, or the highest unprotected memory address, check the busy
status using either the hardware or software (RDSR instruction) method to check for program comple-
tion. Once programming is complete, use the applicable method to terminate AAI. If the device is in
Software End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction, 04H. If the
device is in AAI Hardware End-of-Write Detection mode, execute the Write-Disable (WRDI) instruction,
04H, followed by the 8-bit DBSY command, 80H. There is no wrap mode during AAI programming
once the highest unprotected memory address is reached. See Figures 10 and 11 for the AAI Word
programming sequence.
End-of-Write Detection
There are three methods to determine completion of a program cycle during AAI Word programming:
hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Soft-
ware Status Register, or wait T
BP.
The Hardware End-of-Write detection method is described in the
section below.
Hardware End-of-Write Detection
The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the
Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures
the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming. (see Figure 8)
The 8-bit command, 70H, must be executed prior to initiating an AAI Word-Program instruction. Once
an internal programming operation begins, asserting CE# will immediately drive the status of the inter-
nal flash status on the SO pin. A ‘0’ indicates the device is busy and a ‘1’ indicates the device is ready
for the next instruction. De-asserting CE# will return the SO pin to tri-state. While in AAI and Hardware
End-of-Write detection mode, the only valid instructions are AAI Word (ADH) and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first execute WRDI instruction, 04H, to reset the Write-
Enable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/
BY# status during the AAI command. See Figures 9 and 10.
©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
15
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Figure 8: Enable SO as Hardware RY/BY# During AAI Programming
Figure 9: Disable SO as Hardware RY/BY# During AAI Programming
CE#
SO
SI
SCK
01234567
70
HIGH IMPEDANCE
MODE 0
MODE 3
1417 EnableSO.0
MSB
CE#
SO
SI
SCK
01234567
80
HIGH IMPEDANCE
MODE 0
MODE 3
1417 DisableSO.0
MSB

SST25VF020B-80-4C-Q3AE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7V to 3.6V 2Mbit SPI Serial Flash
Lifecycle:
New from this manufacturer.
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