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SST25VF020B-80-4C-Q3AE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
4
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Pin Description
Figure 2: Pin Assignments
Table 1: Pin Description
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/
BY# pin. See “Hardware End-of-Write Detection” on page 14 for details.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg-
ister.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without reset-
ting the device.
V
DD
Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF020B
V
SS
Ground
T1.0 25054
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
V
DD
HOLD#
SCK
SI
Top View
1417 08-soic S2A P1.0
8-Lead SOIC
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
Top View
V
DD
HOLD#
SCK
SI
1417 08-wson QA P2.0
8-Contact WSON
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
Top View
V
DD
HOLD#
SCK
SI
1417 08-uson Q3A P1.0
8-Contact USON
©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
5
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Memory Organization
The SST25VF020B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
Device Operation
The SST25VF020B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF020B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
Figure 3: SPI Protocol
1417 SPIprot.0
MODE 3
SCK
SI
SO
CE#
MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0MODE 0
HIGH IMPEDANCE
MSB
MSB
©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
6
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Hold Operation
The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without reset-
ting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V
IL
or
V
IH.
If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD#
signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 4 for Hold timing.
Figure 4: Hold Condition Waveform
Write Protection
SST25VF020B provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the sta-
tus register, and the Top/Bottom Sector Protection Status bits (TSP and BSP) in Status Register 1, pro-
vide Write protection to the memory array and the status register. See Table 5 for the Block-Protection
description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined
by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is
disabled.
Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction
WP# BPL Execute WRSR Instruction
L 1 Not Allowed
L 0 Allowed
H X Allowed
T2.0 25054
Active Hold Active Hold Active
1417 HoldCond.0
SCK
HOLD#
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

SST25VF020B-80-4C-Q3AE

Mfr. #:
Buy SST25VF020B-80-4C-Q3AE
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7V to 3.6V 2Mbit SPI Serial Flash
Lifecycle:
New from this manufacturer.
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