©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
18
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-
Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruc-
tion clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected mem-
ory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.
CE# must remain active low for the duration of any command sequence. The 32-KByte Block-Erase
instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A
23
-A
0
]. Address
bits [A
MS
-A
15
] (A
MS
= Most Significant Address) are used to determine block address (BA
X
), remaining
address bits can be V
IL
or V
IH.
CE# must be driven high before the instruction is executed. The 64-KByte Block-
Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits [A
23
-A
0
]. Address bits
[A
MS
-A
15
] are used to determine block address (BA
X
), remaining address bits can be V
IL
or V
IH.
CE# must be
driven high before the instruction is executed. The user may poll the Busy bit in the software status register or
wait T
BE
for the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 13 and 14 for the 32-KByte Block-Erase and 64-KByte Block-Erase sequences.
Figure 13:32-KByte Block-Erase Sequence
Figure 14:64-KByte Block-Erase Sequence
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
52
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
1417 32KBklEr.0
MSB MSB
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
1417 63KBlkEr.0
MSB MSB
