©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
22
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status
register. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and
WRSR for byte-data input sequences.
Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to
“1”. When the WP# is low, the BPL bit can only be set from “0” to “1” to lock-down the status register,
but cannot be reset from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled
and the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0
or WP# pin is driven high (V
IH
) prior to the low-to-high transition of the CE# pin at the end of the WRSR
instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a sin-
gle WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the
BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP# and BPL
functions.
Figure 20:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and
Write-Status-Register (WRSR) Byte-Data Input Sequence
The Write-Status-Register instruction also writes new values to the Status Register 1. To write values
to Status Register 1, the WRSR sequence needs a word-data input—the first byte being the Status
Register bits, followed by the second byte Status Register 1 bits. CE# must be driven low before the
command sequence of the WRSR instruction is entered and driven high before the WRSR instruction
is executed. See Figure 21 for EWSR or WREN and WRSR instruction word-data input sequences.
Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to
‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status registers,
but cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled
and the BPL, BP0, BP1, TSP, and BSP bits in the status register can all be changed. As long as BPL
bit is set to 0 or WP# pin is driven high (V
IH
) prior to the low-to-high transition of the CE# pin at the end
of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well
as altering the BPL, BP0, BP1, TSP, and BSP bits at the same time. See Table 2 for a summary
description of WP# and BPL functions.
1417 EWSR.0
MODE 3
HIGH IMPEDANCE
MODE 0
STATUS
REGISTER IN
76543210
MSBMSBMSB
01
MODE 3
SCK
SI
SO
CE#
MODE 0
50 or 06
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
