CS61884-IQZ Datasheet CS61884-IQZR, CS61884-IQZ, CS61884-IRZR | P13-P15

CS61884

DS485F3 13

INTL/MOT/CODE

88 H12 I

Motorola/Intel/Coder Mode Select Input

Parallel Host Mode

- When this pin is “Low” the micropro-

cessor interface is configured for operation with Motorola

processors. When this pin is “High” the microprocessor in-

terface is configured for operation with Intel processors.

Hardware Mode

- When the CS61884 is configured for uni-

polar operation, this pin, CODEN

, configures the line

encoding/decoding function. When CODEN

is low,

B8ZS/HDB3 encoders/decoders are enabled for T1/J1 or

E1 operation respectively. When CODEN

is high, AMI en-

coding/decoding is activated. This is done for all eight

channels.

TXOE 114 E14 I

Transmitter Output Enable

Host mode

- Operates the same as in hardware mode. In-

dividual drivers can be set to a high impedance state via

the Output Disable Register (12h) (See Section 14.19 on

page 39).

Hardware Mode

- When TXOE pin is asserted Low, all the

TX drivers are forced into a high impedance state. All other

internal circuitry remains active.

CLKE 115 E13 I

Clock Edge Select

In clock/data recovery mode, setting CLKE “high” will cause

RPOS/RNEG to be valid on the falling edge of RCLK and

SDO to be valid on the rising edge of SCLK. When CLKE is

set “low”, RPOS/RNEG is valid on the rising edge of RCLK,

and SDO is valid on the falling edge of SCLK. When the

part is operated in data recovery mode, the RPOS/RNEG

output polarity is active “high” when CLKE is set “high” and

active “low” when CLKE is set “low”.

SYMBOL LQFP LFBGA TYPE DESCRIPTION

CS61884

14 DS485F3

3.3 Address Inputs/Loopbacks

SYMBOL LQFP LFBGA TYPE DESCRIPTION

A4 12 F4 I

Address Selector Input

Parallel Host Mode

- During non-multiplexed parallel host

mode operation, this pin function as the address 4 input for

the parallel interface.

Hardware Mode

- The A4 pin must be tied low at all times.

Non-Intrusive Monitoring/Address Selector Inputs

Parallel Host Mode

- During non-multiplexed parallel host

mode operation, these pins function as address A[3:0] in-

puts for the parallel interface.

Hardware Mode

- The A[3:0] pins are used for port selec-

tion during non-intrusive monitoring. In non-intrusive

monitoring mode, receiver 0’s input is internally connected

to the transmit or receive ports on one of the other 7 chan-

nels. The recovered clock and data from the selected port

are output on RPOS0/RNEG0 and RCLK0. Additionally, the

data from the selected port can be output on

TTIP0/TRING0 by activating the remote loopback function

for channel 0 (Refer to Performance Monitor Register

(0Bh) (See Section 14.12 on page 36).

LOOP0/D0

LOOP1/D1

LOOP2/D2

LOOP3/D3

LOOP4/D4

LOOP5/D5

LOOP6/D6

LOOP7/D7

I/O

Loopback Mode Selector/Parallel Data Input/Output

Parallel Host Mode

- In non-multiplexed microprocessor in-

terface mode, these pins function as the bi-directional 8-bit

data port. When operating in multiplexed microprocessor in-

terface mode, these pins function as the address and data

inputs/outputs.

Hardware Mode

- No Loopback - The CS61884 is in a normal operating

state when LOOP is left open (unconnected) or tied to

VCCIO/2.

- Local Loopback - When LOOP is tied High, data transmit-

ted on TTIP and TRING is looped back into the analog

input of the corresponding channel’s receiver and output on

RPOS and RNEG. Input Data present on RTIP and RRING

is ignored.

- Remote Loopback - When LOOP is tied Low the recov-

ered clock and data received on RTIP and RRING is looped

back for transmission on TTIP and TRING. Data on TPOS

and TNEG is ignored.

CS61884

DS485F3 15

3.4 Cable Select

3.5

Status

SYMBOL LQFP LFBGA TYPE DESCRIPTION

CBLSEL 93 G13 I

Cable Impedance Select

Host Mode

- The input voltage to this pin does not effect

normal operation.

Hardware Mode

- This pin is used in combination with the

LEN control pins (Refer to Table 5, “Hardware Mode Line

Length Configuration Selection,” on page 25) to set the line

impedance for all eight receivers and transmitters. This pin

also selects whether or not all eight receivers use an inter-

nal or external line matching network (Refer to the Table

below for proper settings).

NOTE: Refer to Figure 17 on page 51 and Figure 18 on

page 52 for appropriate external line matching com-

ponents. All transmitters use internal matching net-

works.

Table 3. Cable Impedance Selection

E1/T1/J1 CBLSEL Transmitters Receivers

T1/J1 No Connect 100 Ω Internal Internal

T1/J1 HIGH 100 Ω Internal Internal

T1/J1 LOW 100 Ω Internal External

E1 No Connect 120 Ω Internal Inter or Ext

E1 HIGH 75 Ω Internal Internal

E1 LOW 75 Ω Internal External

SYMBOL LQFP LFBGA TYPE DESCRIPTION

LOS0

LOS1

LOS2

LOS3

LOS4

LOS5

LOS6

LOS7

113

106

140

K12

K11

E11

E12

Loss of Signal Output

The LOS output pins can be configured to indicate a loss of

signal (LOS) state that is compliant to either T1.231, ITU

G.775 or ETSI 300 233. These pins are asserted “High” to

indicate LOS. The LOS output returns low when an input

signal is present for the time period dictated by the associ-

ated specification (Refer to Loss-of-Signal (LOS) (See

Section 10.5 on page 27)).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72

CS61884-IQZ

Mfr. #:

Buy CS61884-IQZ

Manufacturer:

Cirrus Logic

Description:

Telecom Interface ICs IC Octal T1/E1/J1 Line Interface Unit

Lifecycle:

New from this manufacturer.

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CS61884-IQZ

CS61884-IQZ

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