CS61884-IQZ Datasheet CS61884-IQZR, CS61884-IQZ, CS61884-IRZR | P37-P39

CS61884

DS485F3 37

14.13 Digital Loopback Reset Register (0Ch)

14.14 LOS/AIS Mode Enable Register (0Dh)

14.15 Automatic TAOS Register (0Eh)

[3:0] A[3:0]

The G.772 Monitor is directed to a given channel based on the state of the four least signifi-

cant bits of this register. Register bits default to 00h after power-up or reset. The follow-

ing table shows the settings needed to select a specific channel’s receiver or transmitter to

perform G.772 monitoring.

A[3:0] Channel Selection

0000 Monitoring Disabled

0001 RX Channel #1

0010 RX Channel #2

0011 RX Channel #3

0100 RX Channel #4

0101 RX Channel #5

0110 RX Channel #6

0111 RX Channel #7

1000 Monitoring Disabled

1001 TX Channel #1

1010 TX Channel #2

1011 TX Channel #3

1100 TX Channel #4

1101 TX Channel #5

1110 TX Channel #6

1111 TX Channel #7

BIT NAME Description

[7:0] DLBK 7-0 Setting register bit n to “1” enables the digital loopback for channel n. Refer to Digital Loop-

back (See Section 12.3 on page 30) for a complete explanation. Register bits default to

00h after power-up or reset.

BIT NAME Description

[7:0] LAME 7-0 T1/J1 MODE

- These bits are “Do Not Care”, T1.231 Compliant LOS/AIS already used.

E1 Mode

- Setting bit n to “1” enables ETSI 300 233 compliant LOS/AIS for channel n; set-

ting bit n to “0” enables ITU G.775 compliant LOS/AIS for channel n. Register bits default to

00h after power-up or reset.

BIT NAME Description

[7:0] ATAO 7-0 Setting bit n to “1” enables automatic TAOS generation on channel n when LOS is detected.

(Continued)

BIT NAME Description

CS61884

38 DS485F3

14.16 Global Control Register (0Fh)

14.17 Line Length Channel ID Register (10h)

BIT NAME Description

This register is the global control for the AWG Auto-Increment, Automatic AIS insertion,

encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for

all eight channels. Register bits default to 00h after power-up or reset.

[7] AWG Auto-

Increment

The AWG Auto-Increment bit indicates whether to auto-increment the AWG Phase Address

the phase samples address portion of the address register increments after each read or

write access. This bit must be set before any bit in the AWG Enable register is set, if this

function is required.

[6] RAISEN

On LOS, this bit controls the automatic AIS insertion into all eight receiver paths.

0 = Disabled

1 = Enabled

[5] RSVD RESERVED (This bit must be set to 0.)

[4] CODEN

Line encoding/decoding Selection

0 = B8ZS/HDB3 (T1/J1/E1 respectively)

1 = AMI

[3] FIFO

LENGTH

Jitter Attenuator FIFO length Selection

0 = 32 bits

1 = 64 bits

[2] JACF

Jitter Attenuator Corner Frequency Selection

E1 T1/J1

0 = 1.25Hz 3.78Hz

1 = 2.50Hz 7.56Hz

[1:0] JASEL [1:0]

These bits select the position of the Jitter Attenuator.

BIT NAME Description

[7:3] RSVD 7-3 RESERVED (These bits must be set to 0.)

[2:0] LLID 2-0

The value written to these bits specify the LIU channel for which the Pulse Shape Configura-

tion Data (register 11h) applies. For example, writing a value of a binary 000 to the 3-LSBs

will select channel 0. The pulse shape configuration data for the channel specified in this reg-

ister are written or read through the Line Length Data Register (11h). Register bits default

to 00h after power-up or reset.

JASEL 1 JASEL 0 POSITION

0 0 Disabled

0 1 Transmit Path

1 0 Disabled

1 1 Receive Path

CS61884

DS485F3 39

14.18 Line Length Data Register (11h)

14.19 Output Disable Register (12h)

14.20 AIS Status Register (13h)

14.21 AIS Interrupt Enable Register (14h)

BIT NAME Description

The value written to the 4-LSBs of this register specifies whether the device is operating in

either T1/J1 or E1 modes and the associated pulse shape as shown below is being transmit-

ted. Register bits default to 00h after power-up or reset.

[7:5] RSVD RESERVED (These bits must be set to 0.)

[4] INT_EXTB

This bit specifies the use of internal (Int_ExtB = 1) or external (Int_ExtB = 0) receiver line

matching. The line impedance for both the receiver and transmitter are chosen through the

LEN [3:0] bits in this register.

[3:0] LEN[3:0]

These bits setup the line impedance for both the receiver and the transmitter path and the

desired pulse shape for a specific channel. The channel is selected with the Line Length

Channel ID register (0x10). The following table shows the available transmitter pulse

shapes.

LEN [3:0] Operation

Mode

Line Length Selection Phase Samples

per UI

0000 E1 120Ω 3.0V 12

0001 T1/J1 100Ω DS1, Option A (undershoot) 14

0010 T1/J1 100Ω DS1, Option A (0dB) 14

0011 T1/J1 100Ω 0 - 133Ft (0.6dB) 13

0100 T1/J1 100Ω 133 - 266Ft (1.2dB) 13

0101 T1/J1 100Ω 266 - 399Ft (1.2dB) 13

0110 T1/J1 100Ω 399 - 533Ft (2.4dB) 13

0111 T1/J1 100Ω 533 - 655Ft (3.0dB) 13

1000 E1 75Ω 2.37V 12

BIT NAME Description

[7:0] OENB 7-0 Setting bit n of this register to “1” High-Z the TX output driver on channel n of the device.

BIT NAME Description

[7:0] AISS 7-0 A “1” in bit position n indicates that the receiver has detected an AIS condition on channel n,

which generates an interrupt on the INT

pin. Register bits default to 00h after power-up or

reset.

BIT NAME Description

[7:0] AISE 7-0 This register enables changes in the AIS Status register to be reflected in the AIS Interrupt

Status register, thus causing an interrupt on the INT

pin. Register bits default to 00h after

power-up or reset.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72

CS61884-IQZ

Mfr. #:

Buy CS61884-IQZ

Manufacturer:

Cirrus Logic

Description:

Telecom Interface ICs IC Octal T1/E1/J1 Line Interface Unit

Lifecycle:

New from this manufacturer.

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CS61884-IQZ

CS61884-IQZ

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