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CS61884-IQZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
CS61884
34 DS485F3
13.4 Register Set
The register set available during host mode opera-
tions are presented in Table 9. While the upper
three bits of the parallel address are don’t cares on
the CS61884, they should be set to zero for proper
operation.
Table 9. Host Mode Register Set
REGISTERS BITS
ADDR NAME TYPE 7 6 5 4 3 2 1 0
00h
Revision/IDCODE R IDCODE Refer to Device ID Register (IDR) on page 48
01h
Analog Loopback R/W ALBK 7 ALBK 6 ALBK 5 ALBK 4 ALBK 3 ALBK 2 ALBK 1 ALBK 0
02h
Remote Loopback R/W RLBK 7 RLBK 6 RLBK 5 RLBK 4 RLBK 3 RLBK 2 RLBK 1 RLBK 0
03h
TAOS Enable R/W TAOE 7 TAOE 6 TAOE 5 TAOE 4 TAOE 3 TAOE 2 TAOE 1 TAOE 0
04h
LOS Status R LOSS 7 LOSS 6 LOSS 5 LOSS 4 LOSS 3 LOSS 2 LOSS 1 LOSS 0
05h
DFM Status R DFMS 7 DFMS 6 DFMS 5 DFMS 4 DFMS 3 DFMS 2 DFMS 1 DFMS 0
06h
LOS Interrupt Enable R/W LOSE 7 LOSE 6 LOSE 5 LOSE 4 LOSE 3 LOSE 2 LOSE 1 LOSE 0
07h
DFM Interrupt Enable R/W DFME 7 DFME 6 DFME 5 DFME 4 DFME 3 DFME 2 DFME 1 DFME 0
08h
LOS Interrupt Status R LOSI 7 LOSI 6 LOSI 5 LOSI 4 LOSI 3 LOSI 2 LOSI 1 LOSI 0
09h
DFM Interrupt Status R DFMI 7 DFMI 6 DFMI 5 DFMI 4 DFMI 3 DFMI 2 DFMI 1 DFMI 0
0Ah
Software Reset R/W SRES 7 SRES 6 SRES 5 SRES 4 SRES 3 SRES 2 SRES 1 SRES 0
0Bh
Performance Monitor R/W RSVD RSVD RSVD RSVD A3 A2 A1 A0
0Ch
Digital Loopback R/W DLBK 7 DLBK 6 DLBK 5 DLBK 4 DLBK 3 DLBK 2 DLBK 1 DLBK 0
0Dh
LOS/AIS Mode Enable R/W LAME 7 LAME 6 LAME 5 LAME 4 LAME 3 LAME 2 LAME 1 LAME 0
0Eh
Automatic TAOS R/W ATAO 7 ATAO 6 ATAO 5 ATAO 4 ATAO 3 ATAO 2 ATAO 1 ATAO 0
0Fh
Global Control R/W AI Raisen RSVD Coden FIFO JACF JASEL [1:0]
10h
Line Length Channel ID R/W RSVD RSVD RSVD RSVD RSVD Channel ID
11h
Line Length Data R/W RSVD RSVD RSVD IN_EX LEN[3:0]
12h
Output Disable R/W OENB 7 OENB 6 OENB 5 OENB 4 OENB 3 OENB 2 OENB 1 OENB 0
13h
AIS Status R AISS 7 AISS 6 AISS 5 AISS 4 AISS 3 AISS 2 AISS 1 AISS 0
14h
AIS Interrupt Enable R/W AISE 7 AISE 6 AISE 5 AISE 4 AISE 3 AISE 2 AISE 1 AISE 0
15h
AIS Interrupt Status R AISI 7 AISI 6 AISI 5 AISI 4 AISI 3 AISI 2 AISI 1 AISI 0
16h
AWG Broadcast R/W AWGB 7 AWGB 6 AWGB 5 AWGB 4 AWGB 3 AWGB 2 AWGB 1 AWGB 0
17h
AWG Phase Address R/W Channel Address [2:0] Phase Address [4:0]
18h
AWG Phase Data R/W RSVD Sample Data[6:0]
19h
AWG Enable R/W AWGN 7 AWGN 6 AWGN 5 AWGN 4 AWGN 3 AWGN 2 AWGN 1 AWGN 0
1Ah
AWG Overflow Interrupt Enable R/W AWGE 7 AWGE 6 AWGE 5 AWGE 4 AWGE 3 AWGE 2 AWGE 1 AWGE 0
1Bh
AWG Overflow Interrupt Status R AWGI 7 AWGI 6 AWGI 5 AWGI 4 AWGI 3 AWGI 2 AWGI 1 AWGI 0
1Ch
RESERVED R/W RSVD 6 RSVD 5 RSVD 4 RSVD 3 RSVD 2 RSVD 1 RSVD 0 RSVD 6
1Dh
RESERVED R RSVD 6 RSVD 5 RSVD 4 RSVD 3 RSVD 2 RSVD 1 RSVD 0 RSVD 6
1Eh
BITS Clock Enable R/W BITS 7 BITS 6 BITS 5 BITS 4 BITS 3 BITS 2 BITS 1 BITS 0
1Fh
RESERVED R/W RSVD 7 RSVD 6 RSVD 5 RSVD 4 RSVD 3 RSVD 2 RSVD 1 RSVD 0
CS61884
DS485F3 35
14. REGISTER DESCRIPTIONS
14.1 Revision/IDcode Register (00h)
14.2
Analog Loopback Register (01h)
14.3 Remote Loopback Register (02h)
14.4
TAOS Enable Register (03h)
14.5 LOS Status Register (04h)
14.6 DFM Status Register (05h)
BIT NAME Description
[7:4] REVI 7-4 Bits [7:4] are taken from the least-significant nibble of the Device IDCode, which are 0100.
(Refer to Device ID Register (IDR) (See Section 16.3 on page 48).
[3:0] REVI 3-0
Bits [3:0] are the revision bits from the JTAG IDCODE register, CS61884 Revision A = 0000.
These bits are subject to change with the revision of the device (Refer to Device ID Register
(IDR) (See Section 16.3 on page 48).
BIT NAME Description
[7:0] ALBK 7-0
Enables analog loopbacks. A “1” in bit n enables the loopback for channel n. Refer to Analog
Loopback (See Section 12.2 on page 29) for a complete explanation. Register bits default
to 00h after power-up or reset.
BIT NAME Description
[7:0] RLBK 7-0
Enables remote loopbacks. A “1” in bit n enables the loopback for channel n. Refer to
Remote Loopback (See Section 12.4 on page 30) for a complete explanation. Register bits
default to 00h after power-up or reset.
BIT NAME Description
[7:0] TAOE 7-0 A “1” in bit n of this register turns on the TAOS generator in channel n. Register bits default
to 00h after power-up or reset.
BIT NAME Description
[7:0] LOSS 7-0 Register bit n is read as “1” when LOS is detected on channel n. Register bits default to
00h after power-up or reset.
BIT NAME Description
[7:0] DFMS 7-0 Driver Failure Monitor. The DFM will set bit n to “1” when it detects a short circuit in channel
n. Register bits default to 00h after power-up or reset.
CS61884
36 DS485F3
14.7 LOS Interrupt Enable Register (06h)
14.8 DFM Interrupt Enable Register (07h)
14.9
LOS Interrupt Status Register (08h)
14.10 DFM Interrupt Status Register (09h)
14.11 Software Reset Register (0Ah)
14.12 Performance Monitor Register (0Bh)
BIT NAME Description
[7:0] LOSE 7-0 Any change in a LOS Status Register bits will cause the INT
pin to go low if corresponding bit
in this register is set to “1”. Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:0] DFME 7-0
Enables interrupts for failures detected by the DFM. Any change in a DFM Status Register bit
will cause an interrupt if the corresponding bit is set to “1” in this register. Register bits
default to 00h after power-up or reset.
BIT NAME Description
[7:0] LOSI 7-0
Bit n of this register is set to “1” to indicate a status change in bit n of the LOS Status Regis-
ter. The bits in this register indicate a change in status since the last cleared LOS interrupt.
Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:0] DFMI 7-0
Bit n of this register is set to “1” to indicate a status change in bit n of the DFM Status Regis-
ter. The bits in this register indicate a change in status since the last cleared DFM interrupt.
Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:0] SRES 7-0 Writing to this register initializes all registers to their default settings. Register bits default to
00h after power-up or reset.
BIT NAME Description
[7:4] RSVD 7-4 RESERVED (These bits must be set to 0.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72

CS61884-IQZ

Mfr. #:
Buy CS61884-IQZ
Manufacturer:
Cirrus Logic
Description:
Telecom Interface ICs IC Octal T1/E1/J1 Line Interface Unit
Lifecycle:
New from this manufacturer.
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