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CS61884-IQZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
CS61884
4 DS485F3
16.1.2 Test-Logic-Reset ................................................................................................................... 45
16.1.3 Run-Test-Idle ........................................................................................................................ 45
16.1.4 Select-DR-Scan .................................................................................................................... 46
16.1.5 Capture-DR ........................................................................................................................... 46
16.1.6 Shift-DR ................................................................................................................................ 46
16.1.7 Exit1-DR ................................................................................................................................ 46
16.1.8 Pause-DR ............................................................................................................................. 46
16.1.9 Exit2-DR ................................................................................................................................ 46
16.1.10 Update-DR .......................................................................................................................... 46
16.1.11 Select-IR-Scan .................................................................................................................... 47
16.1.12 Capture-IR .......................................................................................................................... 47
16.1.13 Shift-IR ................................................................................................................................ 47
16.1.14 Exit1-IR ............................................................................................................................... 47
16.1.15 Pause-IR ............................................................................................................................. 47
16.1.16 Exit2-IR ............................................................................................................................... 47
16.1.17 Update-IR ........................................................................................................................... 47
16.2 Instruction Register (IR) ................................................................................................................. 47
16.2.1 EXTEST ................................................................................................................................ 47
16.2.2 SAMPLE/PRELOAD ............................................................................................................. 47
16.2.3 IDCODE ................................................................................................................................ 47
16.2.4 BYPASS ............................................................................................................................... 47
16.3 Device ID Register (IDR) ................................................................................................................ 48
17. BOUNDARY SCAN REGISTER (BSR) ................................................................................................ 48
18. APPLICATIONS .................................................................................................................................... 51
18.1 Transformer specifications ............................................................................................................. 53
18.2 Crystal Oscillator Specifications ..................................................................................................... 53
18.3 Designing for AT&T 62411 ............................................................................................................. 53
18.4 Line Protection ............................................................................................................................... 53
19. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 54
19.1 Absolute Maximum Ratings ............................................................................................................ 54
19.2 Recommended Operating Conditions ............................................................................................ 54
19.3 Digital Characteristics ..................................................................................................................... 55
19.4 Transmitter Analog Characteristics ................................................................................................ 55
19.5 Receiver Analog Characteristics .................................................................................................... 56
19.6 Jitter Attenuator Characteristics ..................................................................................................... 57
19.7 Master Clock Switching Characteristics ...................................................................................
...... 59
19.8 Transmit Switching Characteristics ................................................................................................ 59
19.9 Receive Switching Characteristics ................................................................................................. 59
19.10 Switching Characteristics - Serial Port ......................................................................................... 61
19.11 Switching Characteristics - Parallel Port (Multiplexed Mode) ....................................................... 62
19.12 Switching Characteristics- Parallel Port (Non-multiplexed Mode) ................................................ 65
19.13 Switching Characteristics - JTAG ................................................................................................. 68
20. COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS ........................................................... 69
21. LFBGA PACKAGE DIMENSIONS ........................................................................................................ 70
22. LQFP PACKAGE DIMENSIONS .......................................................................................................... 71
23. ORDERING INFORMATION ................................................................................................................ 72
24. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ........................................... 72
25. REVISION HISTORY ............................................................................................................................. 72
CS61884
DS485F3 5
LIST OF FIGURES
Figure 1. CS61884 144-LQFP Pinout ................................................................................................ 7
Figure 2. CS61884 160-Ball LFBGA Pinout ..................................................................................... 8
Figure 3. G.703 BITS Clock Mode in NRZ Mode ..........................................................................23
Figure 4. G.703 BITS Clock Mode in RZ Mode ............................................................................. 23
Figure 5. G.703 BITS Clock Mode in Remote Loopback ............................................................... 23
Figure 6. Pulse Mask at T1/J1 Interface .......................................................................................... 24
Figure 7. Pulse Mask at E1 Interface ..............................................................................................24
Figure 8. Analog Loopback Block Diagram .................................................................................... 30
Figure 9. Analog Loopback with TAOS Block Diagram ................................................................ 30
Figure 10. Digital Loopback Block Diagram .................................................................................. 31
Figure 11. Digital Loopback with TAOS ........................................................................................ 31
Figure 12. Remote Loopback Block Diagram ................................................................................. 31
Figure 13. Serial Read/Write Format (SPOL = 0) ........................................................................... 33
Figure 14. Arbitrary Waveform UI .................................................................................................. 43
Figure 15. Test Access Port Architecture ........................................................................................ 45
Figure 16. TAP Controller State Diagram ....................................................................................... 46
Figure 17. Internal RX/TX Impedance Matching ............................................................................ 51
Figure 18. Internal TX, External RX Impedance Matching ............................................................ 52
Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 ........................... 58
Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 ............................................ 58
Figure 21. Recovered Clock and Data Switching Characteristics ................................................... 60
Figure 22. Transmit Clock and Data Switching Characteristics ...................................................... 60
Figure 23. Signal Rise and Fall Characteristics ............................................................................... 60
Figure 24. Serial Port Read Timing Diagram .................................................................................. 61
Figure 25. Serial Port Write Timing Diagram ................................................................................. 61
Figure 26. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode ................... 63
Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode ........ 63
Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus .................. 64
Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus ................... 64
Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode ....... 66
Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode ........ 66
Figure 32. Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67
Figure 33. Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode . 67
Figure 34. JTAG Switching Characteristics .................................................................................... 68
CS61884
6 DS485F3
LIST OF TABLES
Table 1. Operation Mode Selection .................................................................................................10
Table 2. Mux/Bits Clock Selection ..................................................................................................11
Table 3. Cable Impedance Selection ................................................................................................15
Table 4. G.772 Address Selection ....................................................................................................22
Table 5. Hardware Mode Line Length Configuration Selection ......................................................25
Table 6. Jitter Attenuator Configurations .........................................................................................28
Table 7. Operational Summary ........................................................................................................29
Table 8. Host Control Signal Descriptions ......................................................................................32
Table 9. Host Mode Register Set .....................................................................................................34
Table 10. JTAG Instructions ............................................................................................................47
Table 11. Boundary Scan Register ...................................................................................................48
Table 12. Transformer Specifications ..............................................................................................53
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72

CS61884-IQZ

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Buy CS61884-IQZ
Manufacturer:
Cirrus Logic
Description:
Telecom Interface ICs IC Octal T1/E1/J1 Line Interface Unit
Lifecycle:
New from this manufacturer.
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