CS61884
46 DS485F3
16.1.4 Select-DR-Scan
This is a temporary controller state.
16.1.5 Capture-DR
In this state, the Boundary Scan Register captures
input pin data if the current instruction is EXTEST
or SAMPLE/PRELOAD.
16.1.6 Shift-DR
In this controller state, the active test data register
connected between TDI and TDO, as determined
by the current instruction, shifts data out on TDO
on each rising edge of TCK.
16.1.7 Exit1-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.8 Pause-DR
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the current
test data register.
16.1.9 Exit2-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.10 Update-DR
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the TAP
controller is in this state and the Boundary Scan
Register is selected, data is latched into the parallel
output of this register from the shift-register path
on the falling edge of TCK. The data held at the
latched parallel output changes only in this state.
1
0
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select- IR-Scan
Capture- IR
Shift-IR
Exit1- IR
Pause-IR
Exit2- IR
Update-IR
0
11
1
1
1
11
1
1
1
11
1
1
0
0
0
0
0
0
0
0
00
0
0
0
1
0
Figure 16. TAP Controller State Diagram
CS61884
DS485F3 47
16.1.11 Select-IR-Scan
This is a temporary controller state. The test data
register selected by the current instruction retains
its previous state.
16.1.12 Capture-IR
In this controller state, the instruction register is
loaded with a fixed value of “01” on the rising edge
of TCK. This supports fault-isolation of the board-
level serial test data path.
16.1.13 Shift-IR
In this state, the shift register contained in the in-
struction register is connected between TDI and
TDO and shifts data one stage towards its serial
output on each rising edge of TCK.
16.1.14 Exit1-IR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.15 Pause-IR
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the instruc-
tion register.
16.1.16 Exit2-IR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.17 Update-IR
The instruction shifted into the instruction register
is latched into the parallel output from the shift-reg-
ister path on the falling edge of TCK. When the
new instruction has been latched, it becomes the
current instruction. The test data registers selected
by the current instruction retain their previous val-
ue.
16.2 Instruction Register (IR)
The 3-bit Instruction register selects the test to be
performed and/or the data register to be accessed.
The valid instructions are shifted in LSB first and
are listed in Table 10:
16.2.1 EXTEST
The EXTEST instruction allows testing of off-chip
circuitry and board-level interconnect. EXTEST
connects the BSR to the TDI and TDO pins.
16.2.2 SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction samples all
device inputs and outputs. This instruction places
the BSR between the TDI and TDO pins. The BSR
is loaded with samples of the I/O pins by the Cap-
ture-DR state.
16.2.3 IDCODE
The IDCODE instruction connects the device iden-
tification register to the TDO pin. The device iden-
tification code can then be shifted out TDO using
the Shift-DR state.
16.2.4 BYPASS
The BYPASS instruction connects a one TCK de-
lay register between TDI and TDO. The instruction
is used to bypass the device.
Table 10. JTAG Instructions
IR CODE INSTRUCTION
000 EXTEST
100 SAMPLE/PRELOAD
110 IDCODE
111 BYPASS
CS61884
48 DS485F3
16.3 Device ID Register (IDR)
Revision section: 0h = Rev A, 1h = Rev B and so on. The device Identification Code [27 - 12] is derived
from the last three digits of the part number (884). The LSB is a constant 1, as defined by IEEE 1149.1.
17. BOUNDARY SCAN REGISTER (BSR)
The BSR is a shift register that provides access to the digital I/O pins. The BSR is used to read and write
the device pins to verify interchip connectivity. Each pin has a corresponding scan cell in the register. The
pin to scan cell mapping is given in the BSR description shown in Table 11.
NOTE: Data is shifted LSB first into the BSR register.
CS61884 IDCODE REGISTER(IDR)
REVISION DEVICE IDCODE REGISTER MANUFACTURER CODE
3130 2928 27 2625 24 2322 21 2019 18 1716 15 1413 12 11 109876543210
0h 0h 8h 8h 4h 0h Oh 9h
00000000100010000100000011001001
Table 11. Boundary Scan Register
BSR
Bit
Pin
Name
Cell
Type
Bit
Symbol
0 LOS7 O LOS7
1 RNEG7 O RNEG7
2 RPOS7 O RPOS7
3 RCLK7 O RCLK7
4 - Note 2 HIZ7_B
5 TNEG7 I TNEG7
6 TPOS7 I TPOS7
7 TCLK7 I TCLK7
8 LOS6 O LOS6_B
9 RNEG6 O RNEG6
10 RPOS6 O RPOS6
11 RCLK6 O RCLK6
12 - Note 2 HIZ6_B
13 TNEG6 I TNEG6
14 TPOS6 I TPOS6
15 TCLK6 I TCLK6
16 MCLK I MCLK
17 MODE I MODE_TRI
18 MODE I MODE_IN
19 ADDR4 I ADDR4
20 ADDR3 I ADDR3
21 ADDR2 I ADDR2
22 ADDR1 I ADDR1
23 ADDR0 I ADDR0
24 LOOP0/D0 I LPT0
25 LOOP0/D0 I LPI0
26 LOOP0/D0 O LPO0
27 LOOP1/D1 I LPT1

CS61884-IQZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Telecom Interface ICs IC Octal T1/E1/J1 Line Interface Unit
Lifecycle:
New from this manufacturer.
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