SL811HST-AXC Datasheet SL811HST-AXC | P1-P3

SL811HS

Embedded USB Host/Slave Controller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-08008 Rev. *H Revised April 14, 2014

Features

■ First USB Host/Slave controller for embedded systems in the

market with a standard microprocessor bus interface

■ Supports both full speed (12 Mbps) and low speed (1.5 Mbps)

USB transfer in both master and slave modes

■ Conforms to USB Specification 1.1 for full- and low speed

■ Operates as a single USB host or slave under software control

■ Automatic detection of either low- or full speed devices

■ 8-bit bidirectional data, port I/O (DMA supported in slave mode)

■ On-chip SIE asnd USB transceivers

■ On-chip single root HUB support

■ 256-byte internal SRAM buffer

■ Ping-pong buffers for improved performance

■ Operates from 12 or 48 MHz crystal or oscillator (built-in DPLL)

■ 5 V-tolerant interface

■ Suspend/resume, wake up, and low-power modes are

supported

■ Auto-generation of SOF and CRC5/16

■ Auto-address increment mode, saves memory READ/WRITE

cycles

■ Development kit including source code drivers is available

■ 3.3 V power source, 0.35 micron CMOS technology

■ Available in 48-pin TQFP package

Introduction

The SL811HS is an Embedded USB Host/Slave Controller

capable of communicating in either full speed or low speed. The

SL811HS interfaces to devices such as microprocessors, micro-

controllers, DSPs, or directly to a variety of buses such as ISA,

PCMCIA, and others. The SL811HS USB Host Controller

conforms to USB Specification 1.1.

The SL811HS incorporates USB Serial Interface functionality

along with internal full or low speed transceivers. The SL811HS

supports and operates in USB full speed mode at 12 Mbps, or in

low speed mode at 1.5 Mbps. When in host mode, the SL811HS

is the master and controls the USB bus and the devices that are

connected to it. In peripheral mode, otherwise known as a slave

device, the SL811HS operates as a variety of full- or low speed

devices.

The SL811HS data port and microprocessor interface provide an

8-bit data path I/O or DMA bidirectional, with interrupt support to

allow easy interface to standard microprocessors or

microcontrollers such as Motorola or Intel CPUs and many

others. The SL811HS has 256-bytes of internal RAM which is

used for control registers and data buffer.

The available lead-free package is a 48-pin (SL811HST-AXC)

package. All packages operate at 3.3 VDC. The I/O interface

logic is 5 V-tolerant.

X1 X2

D-

INTR

nWR

nRD

nCS

nRST

D0-7

GENERATOR

USB

Root

HUB

XCVRS

SERIAL

INTERFACE

ENGINE

256 Byte RAM

BUFFERS

CONTROL

REGISTERS

INTERRUPT

CLOCK

CONTROLLER

PROCESSOR

INTERFACE

Master/Slave

Controller

nDRQ

nDACK

DMA

Interface

Logic Block Diagram

Errata: For information on silicon errata, see “Errata” on page 33. Details include trigger conditions, devices affected, and proposed workaround.

SL811HS

Document Number: 38-08008 Rev. *H Page 2 of 39

Contents

Functional Overview ........................................................3

Data Port, Microprocessor Interface ............................3

DMA Controller (slave mode only) ..............................3

Interrupt Controller ......................................................3

Buffer Memory .............................................................4

PLL Clock Generator ...................................................5

USB Transceiver .........................................................6

SL811HS Registers ...........................................................6

Physical Connections ....................................................21

48-Pin TQFP Physical Connections ..........................21

Electrical Specifications ................................................24

Absolute Maximum Ratings .......................................24

Recommended Operating Condition ........................24

External Clock Input Characteristics (X1) ..................24

DC Characteristics ....................................................25

USB Host Transceiver Characteristics ......................25

Bus Interface Timing Requirements ..........................26

Ordering Information ......................................................30

Ordering Code Definitions .........................................30

Package Diagram ............................................................31

Acronyms ........................................................................32

Document Conventions .................................................32

Units of Measure .......................................................32

Errata ...............................................................................33

Part Numbers Affected ..............................................33

SL811HS/SL811 Qualification Status ........................33

SL811HS/SL811 Errata Summary ............................33

Document History Page .................................................37

Sales, Solutions, and Legal Information ......................39

Worldwide Sales and Design Support ....................... 39

Products .................................................................... 39

PSoC® Solutions ......................................................39

Cypress Developer Community .................................39

Technical Support .....................................................39

SL811HS

Document Number: 38-08008 Rev. *H Page 3 of 39

Functional Overview

Data Port, Microprocessor Interface

The SL811HS

[1]

microprocessor interface provides an 8-bit

bidirectional data path along with appropriate control lines to

interface to external processors or controllers. Programmed I/O

or memory mapped I/O designs are supported through the 8-bit

interface, chip select, read and write input strobes, and a single

address line, A0.

Access to memory and control register space is a simple two

step process, requiring an address Write with A0 = ’0’, followed

by a register/memory Read or Write cycle with address line

A0 = ’1’.

In addition, a DMA bidirectional interface in slave mode

[2]

available with handshake signals such as nDRQ, nDACK, nWR,

nRD, nCS and INTRQ.

The SL811HS WRITE or READ operation terminates when

either nWR or nCS goes inactive. For devices interfacing to the

SL811HS that deactivate the Chip Select nCS before the Write

nWR, the data hold timing must be measured from the nCS and

is the same value as specified. Therefore, both Intel

- and

Motorola-type CPUs work easily with the SL811HS without any

external glue logic requirements.

DMA Controller (slave mode only)

In applications that require transfers of large amounts of data

such as scanner interfaces, the SL811HS provides a DMA

interface. This interface supports DMA READ or WRITE

transfers to the SL811HS internal RAM buffer, it is done through

the microprocessor data bus via two control lines (nDRQ - Data

Request and nDACK - Data Acknowledge), along with the nWR

line and controls the data flow into the SL811HS. The SL811HS

has a count register that allows selection of programmable block

sizes for DMA transfer. The control signals, both nDRQ and

nDACK, are designed for compatibility with standard DMA

interfaces.

Interrupt Controller

The SL811HS interrupt controller provides a single output signal

(INTRQ) that is activated by a number of programmable events

that may occur as result of USB activity. Control and status

registers are provided to allow the user to select single or

multiple events, which generate an interrupt (assert INTRQ) and

let the user view interrupt status. The interrupts are cleared by

writing to the Interrupt Status Register.

Notes

1. Errata: In a noisy environment, the SL811HS has the potential to occasionally miss a packet. Please refer to Errata on page 33 for details on errata and suggested

work-around.

2. Errata: The DMA interface can be unreliable in slave mode. Please refer to Errata on page 33 for details on errata and suggested work-around.

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SL811HST-AXC

Mfr. #:

Buy SL811HST-AXC

Manufacturer:

Cypress Semiconductor

Description:

USB Interface IC 256B HOST COM

Lifecycle:

New from this manufacturer.

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SL811HST-AXC