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SL811HST-AXC

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SL811HS
Document Number: 38-08008 Rev. *H Page 7 of 39
USB Control Registers
Communication and data flow on the USB bus uses the
SL811HS’ USB A-B Control registers. The SL811HS communi-
cates with any USB Device function and any specific endpoint
via the USB-A or USB-B register sets.
The USB A-B Host Control registers are used in an overlapped
configuration to manage traffic on the USB bus. The USB Host
Control register also provides a means to interrupt an external
CPU or microcontroller when one of the USB protocol transac-
tions is completed. Table 1 and Tab le 2 show the two sets of USB
Host Control registers, the ’A’ set and ’B’ set. The two register
sets allow for overlapping operation. When one set of param-
eters is being set up, the other is transferring. On completion of
a transfer to an endpoint, the next operation is controlled by the
other register set.
Note The USB-B register set is used only when SL811HS mode
is enabled by initializing register 0FH.
The SL811HS USB Host Control has two groups of five registers
each which map in the SL811HS memory space. These registers
are defined in the following tables.
Table 2. SL811HS Host Control Registers
Register Name SL811H
SL811HS
(hex) Address
USB-A Host Control Register 00h
USB-A Host Base Address 01h
USB-A Host Base Length 02h
USB-A Host PID, Device Endpoint
(Write)/USB Status (Read)
03h
USB-A Host Device Address
(Write)/Transfer Count (Read)
04h
USB-B Host Control Register 08h
USB-B Host Base Address 09h
USB-B Host Base Length 0Ah
USB-B Host PID, Device Endpoint
(Write)/USB Status (Read)
0Bh
USB-B Host Device Address
(Write)/Transfer Count (Read)
0Ch
SL811HS
Document Number: 38-08008 Rev. *H Page 8 of 39
USB-A/USB-B Host Control Registers [Address = 00h, 08h] .
Once the other SL811HS Control registers are configured (registers 01h-04h or 09h-0Ch) the Host Control register is programmed to
initiate the USB transfer. This register initiates the transfer when the Enable and Arm bit are set as described above.
USB-A/USB-B Host Base Address [Address = 01h, 09h] .
The USB-A/B Base Address is a pointer to the SL811HS memory buffer location for USB reads and writes. When transferring data
OUT (Host to Device), the USB-A and USB-B Host Base Address registers can be set up before setting ARM on the USB-A or USB-B
Host Control register. When using a double buffer scheme, the Host Base Address could be set up with the first buffer used for DATA0
data and the other for DATA1 data.
Table 3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Preamble Data Toggle Bit SyncSOF ISO Reserved Direction Enable Arm
Bit Position Bit Name Function
7 Preamble If bit = ’1’ a preamble token is transmitted before transfer of low speed packet. If bit = ’0’,
preamble generation is disabled.
■ The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only
used to send packets to a low speed device through a hub. To communicate to a full speed
device, this bit is set to ‘0’. For example, when SL811HS communicates to a low speed
device via the HUB:
— Set SL811HS SIE to operate at full speed, i.e., bit 5 of register 05h (Control Register 1)
= ’0’.
— Set bit 6 of register 0Fh (Control Register 2) = ’0’. Set correct polarity of DATA+ and
DATA– state for full speed.
— Set bit 7, Preamble bit, = ’1’ in the Host Control register.
■ When SL811HS communicates directly to a low speed device:
— Set bit 5 of register 05h (Control Register 1) = ’1’.
— Set bit 6 of register 0Fh (Control Register 2) = ’1’, DATA+ and DATA– polarity for low
speed.
— The state of bit 7 is ignored in this mode.
6 Data Toggle Bit ’0’ if DATA0, ’1’ if DATA1 (only used for OUT tokens in host mode).
5 SyncSOF ’1’ = Synchronize with the SOF transfer when operating in FS only.
The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted.
When bit 5 = ‘1’, the next enabled packet is sent after next SOF. If bit 5 = ‘0’ the next packet
is sent immediately if the SIE is free. If operating in low speed, do not set this bit.
4 ISO When set to ’1’, this bit allows Isochronous mode for this packet.
3 Reserved Bit 3 is reserved for future use.
2 Direction When equal to ’1’ transmit (OUT). When equal to ’0’ receive (IN).
1 Enable If Enable = ’1’, this bit allows transfers to occur. If Enable = ’0’, USB transactions are ignored.
The Enable bit is used in conjunction with the Arm bit (bit 0 of this register) for USB transfers.
0 Arm Allows enabled transfers when Arm = ’1’. Cleared to ’0’ when transfer is complete (when
Done Interrupt is asserted).
Table 4. USB-A/USB-B Host Base Address Definition [Address 01h, 09h]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HBADD7 HBADD6 HBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0
SL811HS
Document Number: 38-08008 Rev. *H Page 9 of 39
USB-A/USB-B Host Base Length [Address = 02h, 0Ah].
The USB A/B Host Base Length register contains the maximum packet size transferred between the SL811HS and a slave USB
peripheral. Essentially, this designates the largest packet size that is transferred by the SL811HS. Base Length designates the size
of data packet sent or received. For example, in full speed BULK mode, the maximum packet length is 64 bytes. In ISO mode, the
maximum packet length is 1023 bytes since the SL811HS only has an 8-bit length; the maximum packet size for the ISO mode using
the SL811HS is 255 – 16 bytes (register space). When the Host Base length register is set to zero, a Zero-Length packet is transmitted.
USB-A/USB-B USB Packet Status (Read) and Host PID, Device Endpoint (Write) [Address = 03h, 0Bh]. This register has two
modes dependent on whether it is read or written. When read, this register provides packet status and contains information relative
to the last packet that has been received or transmitted. This register is not valid for reading until after the Done interrupt occurs, which
causes the register to update.
When written, this register provides the PID and Endpoint information to the USB SIE engine used in the next transaction.
All 16 Endpoints can be addressed by the SL811HS.
PID[3:0]: 4-bit PID Field (See following table), EP[3:0]: 4-bit Endpoint Value in Binary.
Table 5. USB-A / USB-B Host Base Length Definition [Address 02h, 0Ah]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HBL7 HBL6 HBL5 HBL4 HBL3 HBL2 HBL1 HBL0
Table 6. USB-A/USB-B USB Packet Status Register Definition when READ [Address 03h, 0Bh]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STALL NAK Overflow Setup Sequence Time-out Error ACK
Bit Position Bit Name Function
7 STALL Slave device returned a STALL.
6 NAK Slave device returned a NAK.
5 Overflow Overflow condition - maximum length exceeded during receives. For underflow, see
USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h,
0Ch].
4 Setup This bit is not applicable for Host operation since a SETUP packet is generated by the host.
3 Sequence Sequence bit. ’0’ if DATA0, ’1’ if DATA1.
2 Time-out Timeout occurred. A timeout is defined as 18-bit times without a device response (in full
speed).
1 Error Error detected in transmission. This includes CRC5, CRC16, and PID errors.
0 ACK Transmission Acknowledge.
Table 7. USB-A / USB-B Host PID and Device Endpoint Register when WRITTEN [Address 03h, 0Bh]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0
PID TYPE D7-D4
SETUP 1101 (D Hex)
IN 1001 (9 Hex)
OUT 0001 (1 Hex)
SOF 0101 (5 Hex)
PREAMBLE 1100 (C Hex)
NAK 1010 (A Hex)
STALL 1110 (E Hex)
DATA0 0011 (3 Hex)
DATA1 1011 (B Hex)
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SL811HST-AXC

Mfr. #:
Buy SL811HST-AXC
Manufacturer:
Cypress Semiconductor
Description:
USB Interface IC 256B HOST COM
Lifecycle:
New from this manufacturer.
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