SL811HST-AXC Datasheet SL811HST-AXC | P13-P15

SL811HS

Document Number: 38-08008 Rev. *H Page 13 of 39

Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE register providing interrupt

status. Interrupts are cleared by writing to this register. To clear a specific interrupt, the register is written with corresponding bit set

to ’1’.

Current Data Set Register/Hardware Revision/SOF Counter LOW [Address = 0Eh]. This register has two modes. Read from this

Writing to this register sets up auto generation of SOF to all connected peripherals. This counter is based on the 12 MHz clock and

is not dependent on the crystal frequency. To set up a 1 ms timer interval, the software must set up both SOF counter registers to the

proper values.

Table 14. Interrupt Status Register [Address 0Dh]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

D+ Device

Detect/Resume

Insert/Remove SOF timer Reserved Reserved USB-B USB-A

Bit Position Bit Name Function

7 D+ Value of the Data+ pin.

Bit 7 provides continuous USB Data+ line status. Once it is determined that a device

is inserted (as described below) with bits 5 and 6, bit 7 is used to detect if the inserted

device is low speed (0) or full speed (1).

6 Device Detect/Resume Device Detect/Resume Interrupt.

Bit 6 is shared between Device Detection status and Resume Detection interrupt.

When bit-6 of register 05h is set to one, this bit is the Resume detection Interrupt bit.

Otherwise, this bit is used to indicate the presence of a device, ’1’ = device ‘Not present’

and ’0’ = device ‘Present.’ In this mode, check this bit along with bit 5 to determine

whether a device has been inserted or removed.

5 Insert/Remove Device Insert/Remove Detection.

Bit 5 is provided to support USB cable insertion/removal for the SL811HS in host mode.

This bit is set when a transition from SE0 to IDLE (device inserted) or from IDLE to

SE0 (device removed) occurs on the bus.

4 SOF timer ‘1’ = Interrupt on SOF Timer.

3 Reserved ‘0’

2 Reserved ‘0’

1 USB-B USB-B Done Interrupt. (See description in Interrupt Enable Register [address 06h].)

0 USB-A USB-A Done Interrupt. (See description in Interrupt Enable Register [address 06h].)

Table 15. Hardware Revision when Read [Address 0Eh]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Hardware Revision Reserved

Bit Position Bit Name Function

7-4 Hardware Revision SL811HS rev1.2 Read = 1H; SL811HS rev1.5 Read = 2.

3-2 Reserved Read is zero.

1-0 Reserved Reserved for slave.

SL811HS

Document Number: 38-08008 Rev. *H Page 14 of 39

Example: To set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h.

SOF Counter High/Control Register 2 [Address = 0Fh]. When read, this register returns the value of the SOF counter divided by

64. The software must use this register to determine the available bandwidth in the current frame before initiating any USB transfer.

In this way, the user is able to avoid babble conditions on the USB. For example, to determine the available bandwidth left in a frame

do the following.

Maximum number of clock ticks in 1 ms time frame is 12000 (1 count per 12 MHz clock period, or approximately 84 ns.) The value

read back in Register 0FH is the (count × 64) × 84 ns = time remaining in current frame. USB bit time = one 12 MHz period.

Value of register 0FH Available bit times left are between

BBH 12000 bits to 11968 (187 × 64) bits

BAH 11968 bits to 11904 (186 × 64) bits

Note: Any write to the 0Fh register clears the internal frame counter. Write register 0Fh at least once after power-up. The internal

frame counter is incremented after every SOF timer tick. The internal frame counter is an 11-bit counter, which is used to track the

frame number. The frame number is incremented after each timer tick. Its contents are transmitted to the slave every millisecond in

a SOF packet.

When writing to this register the bits definition are defined as follows.

Note Any write to Control register 0Fh enables the SL811HS full

features bit. This is an internal bit of the SL811HS that enables

additional features.

The USB-B register set is used when SL811HS full feature bit is

enabled.

Example. To set up host to generate 1 ms SOF time:

The register 0Fh contains the upper 6 bits of the SOF timer.

timer is based on an internal 12 MHz clock and uses a counter,

which counts down to zero from an initial value. To set the timer

for 1 ms time, the register 0Eh is loaded with value E0h and

0 of register 05h (Control Register 1) is set to ’1’, which enables

hardware SOF generation. To load both HIGH and LOW

registers with the proper values, the user must follow this

sequence:

1. Write E0h to register 0Eh. This sets the lower byte of the SOF

counter

2. Write AEh to register 0Fh, AEh configures the part for full

speed (no change of polarity) Host with bits 5–0 = 2Eh for

upper portion of SOF counter.

3. Enable bit 0 in register 05h. This enables hardware generation

of SOF.

4. Set the ARM bit at address 00h. This starts the SOF

generation.

Table 16. SOF Counter LOW Address when Written [Address 0Eh]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0

Table 17. SOF High Counter when Read [Address 0Fh]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C13 C12 C11 C10 C9 C8 C7 C6

Table 18. Control Register 2 when Written [Address 0Fh]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SL811HS

Master/Slave

selection

SL811HS

D+/D– Data

Polarity Swap

SOF High Counter Register

Bit Position Bit Name Function

7 SL811HS Master/Slave selection Master = 1, Slave = 0.

6 SL811HS D+/D– Data Polarity Swap ’1’ = change polarity (low speed)

’0’ = no change of polarity (full speed).

5-0 SOF High Counter Register Write a value or read it back to SOF High Counter Register.

SL811HS

Document Number: 38-08008 Rev. *H Page 15 of 39

When in slave mode, the registers in the SL811HS are divided

into two major groups. The first group contains Endpoint regis-

ters that manage USB control transactions and data flow. The

second group contains the USB Registers that provide the con-

trol and status information for all other operations.

Endpoint Registers

Communication and data flow on USB is implemented using

endpoints. These uniquely identifiable entities are the terminals

of communication flow between a USB host and USB devices.

Each USB device is composed of a collection of independently

operating endpoints. Each endpoint has a unique identifier,

which is the Endpoint Number. For more information, see USB

Specification 1.1 section 5.3.1.

The SL811HS supports four endpoints numbered 0–3. Endpoint

0 is the default pipe and is used to initialize and generically

manipulate the device to configure the logical device as the

Default Control Pipe. It also provides access to the device's

configuration information, allows USB status and control access,

and supports control transfers.

Endpoints 1–3 support Bulk, Isochronous, and Interrupt

transfers. Endpoint 3 is supported by DMA. Each endpoint has

two sets of registers—the 'A' set and the 'B' set. This allows

overlapped operation where one set of parameters is set up and

the other is transferring. Upon completion of a transfer to an

endpoint, the ‘next data set’ bit indicates whether set 'A' or set 'B'

is used next. The ‘armed’ bit of the next data set indicates

whether the SL811HS is ready for the next transfer without inter-

ruption.

Endpoints 0–3 Register Addresses

Each endpoint set has a group of five registers that are mapped

within the SL811HS memory. The register sets have address

assignments Endpoint 0-3 Register Addresses as shown in the

following table.

For each endpoint set (starting at address Index = 0), the

registers are mapped as shown in the following table.

Table 19. SL811HS Slave Mode Registers

Endpoint specific register addresses

EP 0 – A EP 0 - B EP 1 – A EP 1 - B EP 2 - A EP 2 - B EP 3 - A EP 3 - B

EP Control Register 00h 08h 10h 18h 20h 28h 30h 0x38

EP Base Address Register 01h 09h 11h 19h 21h 29h 31h 0x39

EP Base Length Register 02h 0Ah 12h 1Ah 22h 2Ah 0x32 0x3A

EP Packet Status Register 03h 0Bh 13h 1Bh 23h 2Bh 0x33 0x3B

EP Transfer Count Register 04h 0Ch 14h 1Ch 24h 2Ch 0x34 0x3C

Control Register 1 05h Interrupt Status Register 0Dh

Interrupt Enable Register 06h Current Data Set Register 0Eh

USB Address Register 07h Control Register 2 0Fh

SOF Low Register (read only) 15h Reserved 1Dh1Fh

SOF High Register (read only) 16h Reserved 25h-27h

Reserved 17h Reserved 2Dh-2Fh

DMA Total Count Low Register 35h

DMA Total Count High Register 36h

Reserved 37h

Memory Buffer 40h – FFh

Table 20. Endpoint 0-3 Register Addresses

Endpoint Register Set Address (in Hex)

Endpoint 0 – a 00 - 04

Endpoint 0 – b 08 - 0C

Endpoint 1 – a 10 - 14

Endpoint 1 – b 18 - 1C

Endpoint 2 – a 20 - 24

Endpoint 2 – b 28 - 2C

Endpoint 3 – a 30 - 34

Endpoint 3 – b 38 - 3C

Table 21. Endpoint Register Indices

Endpoint Register Sets

(for Endpoint n starting at register position Index=0)

Index Endpoint n Control

Index + 1 Endpoint n Base Address

Index + 2 Endpoint n Base Length

Index + 3 Endpoint n Packet Status

Index + 4 Endpoint n Transfer Count

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39

SL811HST-AXC

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Manufacturer:

Cypress Semiconductor

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USB Interface IC 256B HOST COM

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SL811HST-AXC