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SL811HST-AXC

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SL811HS
Document Number: 38-08008 Rev. *H Page 10 of 39
USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register has two
different functions depending on whether it is read or written. When read, this register contains the number of bytes remaining (from
Host Base Length value) after a packet is transferred. For example, if the Base Length register is set to 0x040 and an IN Token was
sent to the peripheral device. If, after the transfer is complete, the value of the Host Transfer Count is 0x10, the number of bytes
actually transferred is 0x30. This is considered as an underflow indication.
When written, this register contains the USB Device Address with which the Host communicates.
DA6-DA0 Device address, up to 127 devices can be addressed.
DA7 Reserved bit must be set to zero.
SL811HS Control Registers
The next set of registers are the Control registers and control more of the operation of the chip instead of USB packet type of transfers.
Table 10 is a summary of the control registers.
Table 8. USB-A / USB-B Host Transfer Count Register when READ [Address 04h, 0Ch]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HTC7 HTC6 HTC5 HTC4 HTC3 HTC2 HTC1 HTC0
Table 9. USB-A / USB-B USB Address when WRITTEN [Address 04h, 0Ch]
Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0
0 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Table 10. Control Registers Summary
Register Name SL811H SL811HS (hex) Address
Control Register 1 05h
Interrupt Enable Register 06h
Reserved Register 07h
Status Register 0Dh
SOF Counter LOW (Write)/HW Revision Register (Read) 0Eh
SOF Counter HIGH and Control Register 2 0Fh
Memory Buffer 10h-FFh
SL811HS
Document Number: 38-08008 Rev. *H Page 11 of 39
Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined as
follows.
At power-up this register is cleared to all zeros.
Low-power Modes [Bit 6 Control Register, Address 05h]
When bit 6 (Suspend) is set to ’1’, the power of the transmit
transceiver is turned off, the internal RAM is in suspend mode,
and the internal clocks are disabled.
Note Any activity on the USB bus (that is, K-State, etc.) resumes
normal operation. To resume normal operation from the CPU
side, a Data Write cycle (i.e., A0 set HIGH for a Data Write cycle)
is done. This is a special case and not a normal direct write
where the address is first written and then the data. To resume
normal operation from the CPU side, you must do a Data Write
cycle only.
Low Speed/Full Speed Modes [Bit 5 Control Register 1,
Address 05h]
The SL811HS is designed to communicate with either full- or low
speed devices. At power-up bit 5 is LOW, i.e., for full speed.
There are two cases when communicating with a low speed
device. When a low speed device is connected directly to the
SL811HS, bit 5 of Register 05h is set to ’1’ and bit 6 of register
0Fh, Polarity Swap, is set to ’1’ in order to change the polarity of
D+ and D–. When a low speed device is connected via a HUB to
SL811HS, bit 5 of Register 05h is set to ’0’ and bit 6 of register
0Fh is set to ’0’ in order to keep the polarity of D+ and D– for full
speed. In addition, make sure that bit 7 of USB-A/USB-B Host
Control registers [00h, 08h] is set to ’1’ for preamble generation.
J-K Programming States [Bits 4 and 3 of Control Register 1,
Address 05h]
The J-K force state control and USB Engine Reset bits are used
to generate a USB reset condition. Forcing K-state is used for
Peripheral device remote wake up, resume, and other modes.
These two bits are set to zero on power-up.
Table 11. Control Register 1 [Address 05h]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved Suspend USB Speed J-K state force USB Engine
Reset
Reserved Reserved SOF ena/dis
Bit Position Bit Name Function
7 Reserved ‘0’
6 Suspend ’1’ = enable, ’0’ = disable.
5 USB Speed ’0’ setup for full speed, ’1’ setup low speed.
4 J-K state force See Table 12.
3 USB Engine Reset USB Engine reset = ’1’. Normal set ’0’.
When a device is detected, the first thing that to do is to send it a USB Reset to force it into
its default address of zero. The USB 2.0 specification states that for a root hub a device
must be reset for a minimum of 50 mS.
2 Reserved Some existing firmware examples set bit 2, but it is not necessary.
1 Reserved ‘0’
0 SOF ena/dis ’1’ = enable auto Hardware SOF generation; ’0’ = disable.
In the SL811HS, bit 0 is used to enable hardware SOF autogeneration. The generation of
SOFs continues when set to ‘0’, but SOF tokens are not output to USB.
Notes
8. Force K-State for low speed.
9. Force J-State for low speed.
Table 12. Bus Force States
USB Engine
Reset
J-K Force
State
Function
0 0 Normal operating mode
0 1 Force USB Reset, D+ and D– are set LOW (SE0)
1 0 Force J-State, D+ set HIGH, D– set LOW
[8]
1 1 Force K-State, D– set HIGH, D+ set LOW
[9]
SL811HS
Document Number: 38-08008 Rev. *H Page 12 of 39
USB Reset Sequence
After a device is detected, write 08h to the Control register (05h)
to initiate the USB reset, then wait for the USB reset time (root
hub should be 50 ms) and additionally some types of devices
such as a Forced J-state. Lastly, set the Control register (05h)
back to 0h. After the reset is complete, the auto-SOF generation
is enabled.
SOF Packet Generation
The SL811HS automatically computes the frame number and
CRC5 by hardware. No CRC or SOF generation is required by
external firmware for the SL811HS, although it can be done by
sending an SOF PID in the Host PID, Device Endpoint register.
To enable SOF generation, assuming host mode is configured:
1. Set up the SOF interval in registers 0x0F and 0x0E.
2. Enable the SOF hardware generation in this register by
setting bit 0 = ‘1’.
3. Set the Arm bit in the USB-A Host Control register.
Interrupt Enable Register [Address = 06h]. The SL811HS
provides an Interrupt Request Output, which is activated for a
number of conditions. The Interrupt Enable register allows the
user to select conditions that result in an interrupt that is issued
to an external CPU through the INTRQ pin. A separate Interrupt
Status register reflects the reason for the interrupt. Enabling or
disabling these interrupts does not have an effect on whether or
not the corresponding bit in the Interrupt Status register is set or
cleared; it only determines if the interrupt is routed to the INTRQ
pin. The Interrupt Status register is normally used in conjunction
with the Interrupt Enable register and can be polled in order to
determine the conditions that initiated the interrupt (See the
description for the Interrupt Status Register). When a bit is set to
’1’ the corresponding interrupt is enabled. So when the enabled
interrupt occurs, the INTRQ pin is asserted. The INTRQ pin is a
level interrupt, meaning it is not deasserted until all enabled inter-
rupts are cleared.
USB Address Register, Reserved, Address [Address = 07h]. This register is reserved for the device USB Address in Slave
operation. It should not be written by the user in host mode.
Registers 08h-0Ch Host-B registers. Registers 08h-0Ch have the same definition as registers 00h-04h except they apply to Host-B
instead of Host-A.
Table 13. Interrupt Enable Register [Address 06h]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved Device
Detect/Resume
Inserted/
Removed
SOF Timer Reserved Reserved USB-B
DONE
USB-A
DONE
Bit Position Bit Name Function
7 Reserved ‘0’
6 Device Detect/Resume Enable Device Detect/Resume Interrupt.
When bit 6 of register 05h (Control Register 1) is equal to ’1’, bit 6 of this register enables
the Resume Detect Interrupt. Otherwise, this bit is used to enable Device Detection
status as defined in the Interrupt Status register bit definitions.
5 Inserted/Removed Enable Slave Insert/Remove Detection is used to enable/disable the device
inserted/removed interrupt.
4 SOF Timer 1 = Enable Interrupt for SOF Timer. This is typically at 1 mS intervals, although the
timing is determined by the SOF Counter high/low registers.
To use this bit function, bit 0 of register 05h must be enabled and the SOF counter
registers 0E hand 0Fh must be initialized.
3 Reserved ‘0’
2 Reserved ‘0’
1 USB-B DONE USB-B Done Interrupt (see USB-A Done interrupt).
0 USB-A DONE USB-A Done Interrupt. The Done interrupt is triggered by one of the events that are
logged in the USB Packet Status register. The Done interrupt causes the Packet Status
register to update.
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SL811HST-AXC

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Buy SL811HST-AXC
Manufacturer:
Cypress Semiconductor
Description:
USB Interface IC 256B HOST COM
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New from this manufacturer.
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