SL811HST-AXC Datasheet SL811HST-AXC | P4-P6

SL811HS

Document Number: 38-08008 Rev. *H Page 4 of 39

Buffer Memory

The SL811HS contains 256 bytes of internal memory used for

USB data buffers, control registers, and status registers. When

in master mode (host mode), the memory is defined where the

first 16 bytes are registers and the remaining 240 bytes are used

for USB data buffers. When in slave mode (peripheral mode), the

first 64 bytes are used for the four endpoint control and status

registers along with the various other registers. This leaves 192

bytes of endpoint buffer space for USB data transfers.

Access to the registers and data memory is through the 8-bit

external microprocessor data bus, in either indexed or direct

addressing. Indexed mode uses the Auto Address Increment

mode described in Auto Address Increment Mode [3], where

direct addressing is used to READ/WRITE to an individual

address.

USB transactions are automatically routed to the memory buffer

that is configured for that transfer. Control registers are provided

so that pointers and block sizes in buffer memory are determined

and allocated.

Figure 1. Memory Map

Auto Address Increment Mode

[3]

The SL811HS supports auto increment mode to reduce READ

and WRITE memory cycles. In this mode, the microcontroller

needs to set up the address only once. Whenever any

subsequent DATA is accessed, the internal address counter

advances to the next address location.

Auto Address Increment Example. To fill the data buffer that is

configured for address 10h, follow these steps:

1. Write 10h to SL811HS with A0 LOW. This sets the memory

address that is used for the next operation.

2. Write the first data byte into address 10h by doing a write

operation with A0 HIGH. An example is a Get Descriptor; the

first byte that is sent to the device is 80h (bmRequestType) so

you would write 80h to address 10h.

3. Now the internal RAM address pointer is set to 11h. So, by

doing another write with A0 HIGH, RAM address location 11h

is written with the data. Continuing with the Get Descriptor

example, a 06h is written to address 11h for the bRequest

value.

4. Repeat Step 3 until all the required bytes are written as

necessary for a transfer. If auto-increment is not used, you

write the address value each time before writing the data as

shown in Step 1.

The advantage of auto address increment mode is that it reduces

the number of required SL811HS memory READ/WRITE cycles

to move data to/from the device. For example, transferring 64

bytes of data to/from SL811HS, using auto increment mode,

reduces the number of cycles to 1 address WRITE and 64

READ/WRITE data cycles, compared to 64 address writes and

64 data cycles for random access.

0x00 – 0x0F Control

and status registers

0x10 – 0xFF

USB data buffer

240 bytes

16 bytes

0x00 – 0x39

Control/status registers

and endpoint

control/status registers

0x40 – 0xFF

USB data buffer

192 bytes

64 bytes

Host Mode Memory Map Peripheral Mode Memory Map

Note

3. Errata: The auto-increment feature can intermittently fail, causing the RAM location to be corrupted or the read buffer to provide incorrect data to the system processor.

Please refer to Errata on page 33 for details on errata and suggested work-around.

SL811HS

Document Number: 38-08008 Rev. *H Page 5 of 39

PLL Clock Generator

Either a 12 MHz

[4]

or a 48 MHz external crystal is used with the

SL811HS

[5]

. Two pins, X1 and X2, are provided to connect a low

cost crystal circuit to the device as shown in Figure 2 and

Figure 2. Use an external clock source if available in the

application instead of the crystal circuit by connecting the source

directly to the X1 input pin. When a clock is used, the X2 pin is

not connected.

When the CM pin is tied to a logic 0, the internal PLL is bypassed

so the clock source must meet the timing requirements specified

by the USB specification.

Figure 2. Full Speed 48 MHz Crystal Circuit

Figure 3. Optional 12 MHz Crystal Circuit

Typical Crystal Requirements

The following are examples of ‘typical requirements.’ Note that

these specifications are generally found as standard crystal

values and are less expensive than custom values. If crystals are

used in series circuits, load capacitance is not applicable. Load

capacitance of parallel circuits is a requirement. 48 MHz third

overtone crystals require the Cin/Lin filter to guarantee 48 MHz

operation.

Cbk

0.01



100X1

48 MHz, series, 20-pF load

Cout

22 pF

Cin

22 pF

Lin

2.2



12 MHz Crystals:

Frequency Tolerance: ±100 ppm or better

Operating Temperature Range: 0 C to 70 C

Frequency: 12 MHz

Frequency Drift over Temperature: ± 50 ppm

ESR (Series Resistance): 60

Load Capacitance: 10 pF min.

Shunt Capacitance: 7 pF max.

Drive Level: 0.1–0.5 mW

Operating Mode: fundamental

48 MHz Crystals:

Frequency Tolerance: ±100 ppm or better

Operating Temperature Range: 0 C to 70 C

Frequency: 48 MHz

Frequency Drift over Temperature: ± 50 ppm

ESR (Series Resistance): 40 

Load Capacitance: 10 pF min.

Shunt Capacitance: 7 pF max.

Drive Level: 0.1–0.5 mW

Operating Mode: third overtone

12 MHz , series, 20-pF load

Cin

22 pF

Cout

22 pF

100

X2X1

Notes

4. Errata: The internal PLL is very sensitive. The PLL causes any high frequency noise on the VDD pins to result in clock jitter. Please refer to Errata on page 33 for

details on errata and suggested work-around.

5. CM (Clock Multiply) pin of the SL811HS must be tied to GND when 48 MHz crystal circuit or 48 MHz clock source is used.

SL811HS

Document Number: 38-08008 Rev. *H Page 6 of 39

USB Transceiver

The SL811HS has a built in transceiver that meets USB

Specification 1.1. The transceiver is capable of transmitting and

receiving serial data at USB full speed

[6]

(12 Mbits) and low

speed

[7]

(1.5 Mbits). The driver portion of the transceiver is

differential while the receiver section is comprised of a differential

receiver and two single-ended receivers. Internally, the

transceiver interfaces to the Serial Interface Engine (SIE) logic.

Externally, the transceiver connects to the physical layer of the

USB.

SL811HS Registers

Operation and control of the SL811HS is managed through

internal registers. When operating in Master/Host mode, the first

16 address locations are defined as register space. In

Slave/Peripheral mode, the first 64 bytes are defined as register

space. The register definitions vary greatly between each mode

of operation and are defined separately in this document (section

Table 1 describes Host register definitions, while Table 19 on

page 15 describes Slave register definitions). Access to the

registers are through the microprocessor interface similar to

normal RAM accesses (see “Bus Interface Timing

Requirements” on page 26) and provide control and status

information for USB transactions.

Any write to control register 0FH enables the SL811HS full

features bit. This is an internal bit of the SL811HS that enables

additional features.

Table 1 shows the memory map and register mapping of the

SL811HS in master/host mode.

The registers in the SL811HS are divided into two major groups.

The first group is referred to as USB Control registers. These

registers enable and provide status for control of USB

transactions and data flow. The second group of registers

provides control and status for all other operations.

The following registers initialize to zero on power-up and reset:

■ USB-A/USB-B Host Control Register [00H, 08H] bit 0 only

■ Control Register 1 [05H]

■ USB Address Register [07H]

■ Current Data Set/Hardware Revision/SOF Counter LOW

All other register’s power-up and reset in an unknown state and

firmware for initialization.

Table 1. SL811HS Master (Host) Mode Registers

SL811HS

(hex) Address

USB-A Host Control Register 00h

USB-A Host Base Address 01h

USB-A Host Base Length 02h

USB-A Host PID, Device Endpoint

(Write)/USB Status (Read)

03h

USB-A Host Device Address

(Write)/Transfer Count (Read)

04h

Control Register 1 05h

Interrupt Enable Register 06h

Reserved Register Reserved

USB-B Host Control Register 08h

USB-B Host Base Address 09h

USB-B Host Base Length 0Ah

USB-B Host PID, Device Endpoint

(Write)/USB Status (Read)

0Bh

USB-B Host Device Address

(Write)/Transfer Count (Read)

0Ch

Status Register 0Dh

SOF Counter LOW (Write)/HW Revision

0Eh

SOF Counter HIGH and Control Register 2 0Fh

Memory Buffer 10H-FFh

Notes

6. Errata: The SYNC to SOF bit (bit 5) of the USB Host Control Registers [00H, 08H], is only designed for full-speed support. In full-speed mode, this bit should only be

used when the software cannot fit a packet within the remaining 1 ms frame. Please refer to Errata on page 33 for details on errata and suggested work-around.

7. Errata: Some hubs that send SE0s upstream during the EOF1 time frame may cause the SL811HS to stop sending SOFs. This problem occurs when operating with

low-speed devices attached downstream of such a hub. Please refer to Errata on page 33 for details on errata and suggested work-around.

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SL811HST-AXC

Mfr. #:

Buy SL811HST-AXC

Manufacturer:

Cypress Semiconductor

Description:

USB Interface IC 256B HOST COM

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