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NCP1910GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
NCP1910
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19
• On Board Dead Time: to eliminate the shoot-through
on the half-bridge leg, a dead time is included in the
controller (see DT
L
parameter).
• Soft-Start: a dedicated pin discharges a capacitor to
ground upon start-up to offer a smooth output voltage
ramp up. The start-up frequency is the maximum set by
the resistor connected between R
t
pin and SS pin.
The capacitor connected from R
t
pin to ground fixes the
soft start duration. In fault mode, when the voltage on
CS/FF pin exceeds a typical value of 1 V, the soft-start
pin is immediately discharged and a re-start at high
frequency occurs.
• Skip Cycle Operation: to avoid any frequency
runaway in light conditions but also to improve the
standby power consumption, the NCP1910B welcomes
a skip input (Skip pin) which permanently observes the
opto-coupler collector. If this pin senses a low voltage,
it cuts the LLC output pulses until the collector goes up
again. The NCP1910A does not offer the skip
capability and routes the analog ground on pin 16
instead.
• High-Soltage Drivers: capitalizing on
ON Semiconductor technology, the LLC controller
includes a high-voltage section allowing a direct
connection to the high-voltage rail. The MOSFET leg
can therefore be directly driven without using
a gate-drive transformer.
• Fault Protection: as explained in the above lines,
the CS/FF pin combines a two-level protection circuit.
If the level crosses the first level (1 V), the LLC
converter immediately increases its switching
frequency to the maximum set by the external resistive
divider connected on R
t
pin. This is an auto-recovery
protection mode. In case the fault is more severe,
the signal on the CS/FF pin crosses the second
threshold (1.5 V) and latches off the whole combo
controller. Reset occurs via an UVLO detection on
V
CC
, a reset on the on/off pin or a brown-out detection
on the PFC stage. This latter confirms that the user has
unplugged and re-plugged the power supply.
Combo Management
• Start-Up Delay: the PFC start-up sequence often
generates an output overshoot followed by damped
oscillations. To make sure the PFC output voltage is
fully stabilized before starting the LLC converter,
a 20 ms delay is inserted after the internal PFC_ok
signal is asserted. This delay is always reset when the
combo is started from a V
CC
ULVO, line brown-out
condition or via the on/off pin.
• Power Good Signal: the power good signal (PG) is
intended to instruct the downstream circuitry installed
on the isolated secondary side that the combo is
working. Once the PFC has started, an internal
“PFC_OK” signal is asserted. 20 ms later, the PG pin is
brought low. This signal can now disappear in two
cases: the bulk voltage decreases to an abnormal level,
programmed by a reference voltage imposed on PG
adj
pin. This level is usually above the LLC turn-off
voltage, programmed by BO
adj
pin. Therefore,
in a normal turn-off sequence, PG first drops and
signals the secondary side that it must be prepared for
shutdown. The second event that can drop the PG
signal is when the PFC experiences a fault: broken
feedback path, severe overload. In this case, the PG
signal is immediately asserted high and a 5 ms timer
starts. Once this timer is elapsed, the LLC converter can
be safely halted.
• Latched Event: in the event of a severe operating
condition, the PFC can be latched (OVP2 pin) and/or
the LLC controller also (CS/FF pin). In either case,
the whole combo controller is locked and can only be
reset via a V
CC
UVLO, line brown-out or a level
transition on pin on/off.
• Thermal Shutdown: an internal thermal circuitry
disables the circuit gate drive and then keeps the power
switch off when the junction temperature exceeds
140°C typically. The circuit resumes operation once the
temperature drops below about 110°C (30°C
hysteresis).
Principle of NCP1910 Scheme
PFC Section
A CCM PFC boost converter is shown in Figure 41.
The input voltage is a rectified 50 Hz or 60 Hz sinusoidal
signal. The MOSFET is switching at a high frequency
(typically 65 kHz in NCP1910) so that the inductor current
I
L
basically consists of high and low-frequency
components.
Filter capacitor C
in
is an essential and very small value
capacitor in order to eliminate the high-frequency
component of the inductor I
L
. This filter capacitor cannot be
too bulky because it can pollute the power factor by
distorting the rectified sinusoidal input voltage.
NCP1910
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20
C
in
R
SENSE
L
I
L
C
bulk
V
in
I
in
Bulk voltage (V
bulk
)
Figure 41. CCM PFC Boost Converter
PFC Methodology
The NCP1910 uses a proprietary PFC methodology
particularly designed for CCM operation. The PFC
methodology is described in this section.
Figure 42. Inductor Current in CCM
As shown in Figure 42, the inductor current I
L
in
a switching period T includes a charging phase for duration
t
1
and a discharging phase for duration t
2
. The voltage
conversion ratio is obtained in Equation 1.
V
bulk
V
in
+
t
1
) t
2
t
2
+
T
T * t
1
(eq. 1)
V
in
+
T * t
1
T
V
bulk
Where:
♦ V
bulk
is the output voltage of PFC stage,
♦ V
in
is the rectified input voltage,
♦ T is the switching period,
♦ t
1
is the MOSFET on time, and
♦ t
2
is the MOSFET off time.
The input filter capacitor C
in
and the front-ended EMI
filter absorbs the high-frequency component of inductor
current I
L
. It makes the input current I
in
a low-frequency
signal only of the inductor current.
I
in
+ I
L−50
(eq. 2)
Where:
♦ I
in
is the input AC current.
♦ I
L
is the inductor current.
♦ I
L−50
supposes a 50 Hz operation. The suffix 50
means it is with a 50 Hz bandwidth of the original
I
L
.
From Equations 1 and 2, the input impedance Z
in
is
formulated.
Z
in
+
V
in
I
in
+
T * t
1
T
V
bulk
I
L*50
(eq. 3)
where: Z
in
is input impedance.
Power factor is corrected when the input impedance Z
in
in
Equation 3 is constant or varies slowly in the 50 or 60 Hz
bandwidth.
Figure 43. PFC Duty Modulation and
Timing Diagram
V
PREF
V
PREF
The PFC modulation and timing diagram is shown in
Figure 43. The MOSFET on time t
1
is generated by the
intersection of reference voltage V
PREF
and ramp voltage
V
ramp
. A relationship in Equation 4 is obtained.
V
ramp
+ V
M
)
I
ch
t
1
C
ramp
+ V
PREF
(eq. 4)
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Where:
♦ V
ramp
is the internal ramp voltage, the positive input
of the PFC modulation comparator,
♦ V
M
is the multiplier voltage appearing on V
M
pin,
♦ I
ch
is the internal charging current,
♦ C
ramp
is the internal ramp capacitor, and
♦ V
PREF
is the internal reference voltage, the negative
input of the PFC modulation comparator.
I
ch
, C
ramp
, and V
PREF
also act as the ramp signal of
switching frequency. Hence the charging current I
ch
is
specially designed as in Equation 5. The multiplier voltage
V
M
is therefore expressed in terms of t
1
in Equation 6.
I
ch
+
C
ramp
V
PREF
T
(eq. 5)
V
M
+ V
PREF
*
t
1
C
ramp
C
ramp
V
PREF
T
+ V
PREF
T * t
1
T
(eq. 6)
From Equation 3 and Equation 6, the input impedance Z
in
is re-formulated in Equation 7.
Z
in
+
V
M
V
PREF
V
bulk
I
L−50
(eq. 7)
Because V
PREF
and V
bulk
are roughly constant versus
time, the multiplier voltage V
M
is designed to be
proportional to the I
L−50
in order to have a constant Z
in
for
PFC purpose. It is illustrated in Figure 44.
Figure 44. Multiplier Voltage Timing Diagram
It can be seen in the timing diagram in Figure 43 that V
M
originally consists of a switching frequency ripple coming
from the inductor current I
L
. The duty ratio can be
inaccurately generated due to this ripple. This modulation is
the so-called “peak current mode”. Hence, an external
capacitor C
M
connected to the multiplier voltage V
M
pin is
essential to bypass the high-frequency component of V
M
.
The modulation becomes the so-called “average current
mode” with a better accuracy for PFC.
11
V
M
PFC Duty
Modulation
R
M
C
M
I
M
Figure 45. The Multiplier Voltage Pin Configuration
V
M
+
R
M
I
CS
ǒ
V
LBO
Ǔ
2
4
ǒ
V
CTRL
* V
CTRL
ǒ
min
Ǔ
Ǔ
The multiplier voltage V
M
is generated according to
Equation 8.
V
M
+
R
M
I
CS
ǒ
V
LBO
Ǔ
2
4
ǒ
V
CTRL
* V
CTRL(min)
Ǔ
(eq. 8)
Where:
♦ R
M
is the external multiplier resistor connected to
V
M
pin, which is constant.
♦ V
LBO
is the input voltage signal appearing on the
LBO pin, which is proportional to the rms input
voltage,
♦ I
CS
is the sense current proportional to the inductor
current I
L
as described in Equation 13.
♦ V
CTRL
is the control voltage signal, the output
voltage of Operational Trans-conductance Amplifier
(OTA), as described in Equation 17.
♦ V
CTRL(min)
is not only the minimum operating
voltage of V
CTRL
but also the offset voltage for the
PFC current modulation.
R
M
directly limits the maximum input power capability.
Also, due to the V
in
2
feed-forward feature, where the V
LBO
is squared, the transfer function and the power delivery is
independent from the ac line level. The relationship between
V
CTRL
and power delivery will be depicted later on.
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NCP1910GEVB

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Manufacturer:
ON Semiconductor
Description:
BOARD DEMO NCP1910DEMO-B-TLS
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