NCP1910
http://onsemi.com
26
Where:
♦ I
Ct(min)
limits the minimum operating frequency.
♦ I
Ct
and I
Ct(min)
provide the charging current for
oscillator and hence control the nominal operating
frequency.
♦ V
fold
determines the power level at which the
frequency foldback starts.
♦ I
Ct(fold)
steals the I
Ct
and hence reduces the
operating frequency according to the error
information between V
fold
and
(V
CTRL
−V
CTRL(min)
).
♦ The transient slope of frequency foldback vs. V
CTRL
is fixed inside.
♦ V
fold(max)
is to limit the maximum power level of
frequency foldback, which is around 2 V typically.
The frequency foldback is disabled at start-up, i.e. before
the PFCok signal in Figure 50 is asserted high.
The user can adjust the power level at which the frequency
foldback starts by adjust the resistor divider between V
REF
pin and fold pin. Also, the frequency foldback can be
disabled by grounding fold pin.
The relationship between operating frequency and V
CTRL
is depicted in Figure 51.
V
CTRL
−V
CTRL(min)
T Power
F
sw(fold)
F
sw
V
fold
V
fold
– 0.4
The slope is fixed internally.
The power level at which fre-
quency starts reducing is ad-
justable by modifying V
fold
.
Figure 51. The Relationship between Frequency and V
FREQUENCY
PFC Power Boost
As depicted in previous section, thanks to the V
in
2
feed-forward, the power delivery is independent from input
voltage. It brings benefit of good power factor and a direct
control on the frequency foldback. However, in some special
case such as when the ac input voltage drops sharply from
high line to low line, the power will be limited because the
filter on LBO pin slows down the reaction speed to follow
up the change on input voltage. In the end, the bulk voltage
might drop too low and stop the LLC converter.
Hence, NCP1910 builds a so-called PFC power boost
function inside. The idea is to pull down LBO pin to 2 V
typically, V
LBO(PD)
, when
• V
LBO
is above 2 V, V
LBO(PD)
, i.e. the input is at high
line, and
• V
CTRL
is at maximum for more than timer defined by
t
PFCflag
, and,
• V
bulk
is under 95% of nominal output, i.e. VLD is
triggered.
The maximum pulling-down duration is defined by
t
LBO(PDlimit)
, which is 5 ms typically. A blanking timer,
t
LBO(PDblank)
, is to avoid this power boost function reacting
too soon, which is about 77 ms typically. The PFC power
boost function is inhibited at start-up until bulk voltage is
above 95% of nominal output.
PFC Skip Mode
In order to ensure a proper regulation in no load
conditions, the circuit skips cycles when V
CTRL
is at its
minimum level. V
CTRL
is maintained between about 0.6 V
and 3.6 V due to the internal active clamps. A skip sequence
occurs as long as the 0.6 V clamp circuitry is triggered and
switching operations is recovered when the clamp is
inactive.
Fast Transient Response
Given the low bandwidth of the regulation block, the
output voltage of PFC stages may exhibit excessive over or
under-shoots because of abrupt load or input voltage
variations (such as start-up duration). As shown in
Figure 52, if the output voltage is out of regulation,
NCP1910 has 2 functions to maintain the output voltage
regulation.
