NCP1910
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22
Line Brown-Out Protection
EMI
Filter
Ac line
R
Q
S
L
reset
reset
reset
BO
Vdd
V
in
R
LBOU
R
LBOL
C
in
R
SENSE
C
LBO
PFC_BO
V
LBOT
I
LBOH
LBO comp.
V
LBOcomp
t
LBO(blank)
t
LBO(window)
V
LBO(clamp)
LBO
Figure 46. The Line Brown-Out Configuration
As shown in Figure 46, the Line Brown-Out pin
(represented LBO pin) as receives a portion of the input
voltage (V
in
). As V
in
is a rectified sinusoid, a capacitor must
integrate the ac line ripple so that a voltage proportional to
the average value of V
in
is applied to the brown-out pin.
The main function of the LBO block is to detect too low
input voltage conditions. A 7 mA current source lowers the
LBO pin voltage when a brown-out condition is detected.
This is for hysteresis purpose as required by this function.
In nominal operation, the voltage applied to LBO pin must
be above the internal reference voltage, V
LBOT
(1 V
typically). In this case, the output of the LBO comparator
V
LBOcomp
is low.
Conversely, if V
LBO
goes below 1 V, V
LBOcomp
turns high
and a 980 mV voltage source, V
LBO(clamp)
, is connected to
the LBO pin to maintain the pin level near 1 V. Then a 50 ms
blanking delay, t
LBO(blank)
, is activated during which no
fault is detected. The main goal of the 50 ms lag is to help
meet the hold-up requirements. In case of a short mains
interruption, no fault is detected and hence, both PFC and
LLC keep operating. In addition, LBO pin being kept at
980 mV, there is almost no extra delay between the line
recovery and the occurrence of a proper voltage applied to
LBO pin, that otherwise would exist because of the large
capacitor typically placed between LBO pin and ground to
filter the input voltage ripple. As a result, the NCP1910
effectively “blanks” any mains interruption that is shorter
than 25 ms (minimum guaranteed value of the 50 ms timer).
At the end of this blanking delay (t
LBO(blank)
), another
timer is activated that sets a 50 ms window during which a
fault can be detected. This is the role of the t
LBO(window)
in
Figure 46:
If V
LBOcomp
is high during the second 50 ms delay
(t
LBO(window)
), a line brown-out condition is confirmed
and PFC_BO signal is asserted high.
If V
LBOcomp
remains low for the duration of the
t
LBO(window)
, no fault is detected.
When the PFC_BO signal is high:
The PFC driver is disabled, and the V
CTRL
pin is
grounded to recover operation with a soft-start when
the fault has gone.
The V
LBO(clamp)
voltage source is removed from LBO
pin.
The I
LBOH
current source (7 mA typically) is enabled
that lowers the LBO pin voltage for hysteresis purpose.
At startup, a pnp transistor ensures that the LBO pin
voltage remains below when: V
CC
< UVLO or ON/OFF pin
is released open or UVP or Thermal Shutdown. This is to
guarantee that the circuit starts operation in the right state,
which is “PFC_BO” high. When the NCP1910 is ready to
work, the pnp transistor turns off and the circuit enables the
I
LBOH
.
Also, I
LBOH
is enabled whenever the part is in off mode,
but at startup, I
LBOH
is disabled until V
CC
reaches V
CC(on)
.
Line Brown-Out Network Calculation
If the line brown-out network is connected to the voltage
after bridge diode, the monitored voltage can be very
different depending on the phase:
Before operation, the PFC stage is off and the input
bridge acts as a peak detector. As a consequence, the
input voltage is approximately flat and nearly equates
NCP1910
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23
the ac line amplitude: <V
in
> = 2 V
ac,rms
, where V
ac,rms
is the rms voltage of the line. As depicted in previous
section, the I
LBOH
turns on before PFC operates for the
purpose of adjustable line brown-out hysteresis; hence,
the average voltage applied to LBO pin is:
V
LBO
+ 2
Ǹ
V
ac,rms
R
LBOL
R
LBOU
) R
LBOL
* I
LBOH
(eq. 9)
@
R
LBOU
@ R
LBOL
R
LBOU
) R
LBOL
V
LBO
] 2
Ǹ
V
ac,rms
R
LBOL
R
LBOU
) R
LBOL
* I
LBOH
R
LBOL
If R
LBOL
<< R
LBOU
,
After the PFC stage has started operation, the input
voltage becomes a rectified sinusoid and the average
voltage becomes <V
in
> = (2/p) 2 V
ac,rms
, which
decays 2/π of the peak value of rms input voltage.
Hence, the average voltage applied to LBO pin is:
<V
LBO
> = (2/p) 2 V
ac,rms
R
LBOL
/(R
LBOU
+ R
LBOL
).
And because of the ripple on the LBO pin, the
minimum value of V
LBO
is around:
V
LBO
+
2
p
2
Ǹ
V
ac,rms
R
LBOL
R
LBOU
) R
LBOL
(eq. 10)
ǒ
1 *
f
LBO
3f
line
Ǔ
Where:
f
LBO
is the sensing network pole frequency.
f
LBO
+
R
LBOU
) R
LBOL
2pR
LBOU
R
LBOL
C
LBO
f
line
is the line frequency.
R
LBOL
is low side resistor of the dividing resistors
between LBO pin and ground.
R
LBOU
is upper side resistor of the dividing resistors
between V
in
and LBO pin.
The term
1 *
f
LBO
3f
line
of Equation 10 enables to take into
account the LBO pin voltage ripple (first approximation).
If as a rule of the thumb, we will assume that
f
LBO
+
f
line
10
.
Re-arranging the Equation 9 and 10, the network connected
to LBO pin can be calculated with the following equations:
R
LBOL
+
ȧ
ȡ
Ȣ
1
1 *
f
LBO
3f
line
@
p
2
@
V
ac,on
V
ac,off
* 1
ȧ
ȣ
Ȥ
@
V
LBOT
I
LBOH
(eq. 11)
^
ǒ
1
0.967
@
p
2
@
V
ac,on
V
ac,off
* 1
Ǔ
@
V
LBOT
I
LBOH
R
LBOU
+
ǒ
2
Ǹ
@ V
ac,on
I
LBOH
R
LBOL
) V
LBOT
* 1
Ǔ
R
LBOL
(eq. 12)
Where:
V
ac,on
is the rms ac voltage to starts PFC operating.
V
ac,off
the rms ac voltage for line brown-out
detection.
PFC Current Sense
GND
CS
NCP1910
I
CS
R
CS
R
SENSE
I
L
+
V
CS
I
L
Figure 47. PFC Current Sensing Configuration
The device senses the inductor current I
L
by the current
sense scheme in Figure 47. The device maintains the voltage
at CS pin to be zero voltage, i.e. V
CS
= 0 V, so that
I
CS
+
R
SENSE
R
CS
I
L
(eq. 13)
Where:
R
SENSE
is the sense resistor to sense I
L
.
R
CS
is the offset resistor between CS pin and
R
SENSE
.
This scheme has the advantage of the minimum number
of components for current sensing. The sense current I
CS
represents the inductor current I
L
and will be used in the PFC
duty modulation to generate the multiplier voltage V
M
,
Over-Power Limitation (OPL), and Over-Current
Protection. Equation 13 would insist in the fact that it
provides the flexibility in the R
SENSE
choice and that it
allows to detect in-rush currents.
PFC Over-Current Protection (OCP)
PFC Over-current Protection is reached when I
CS
is larger
than I
S(OCP)
(200 mA typical). The offset voltage of the CS
pin is typical 10 mV and it is neglected in the calculation.
Hence, the maximum OCP inductor current threshold
I
L(OCP)
is obtained in Equation 14.
I
L
ǒ
OCP
Ǔ
+
R
CS
I
S
ǒ
OCP
Ǔ
R
SENSE
+
R
CS
R
SENSE
200 mA
(eq. 14)
When over-current protection threshold is reached, the
PFC drive goes low. The device automatically resumes
operation when the inductor current goes below the
threshold.
NCP1910
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24
PFC Over-Power Limitation (OPL)
This is a second OCP with a threshold that is line
dependent. Sense current I
CS
represents the inductor current
I
L
and hence represents the input current approximately.
Input voltage signal V
LBO
represents the rms input voltage.
The product (I
CS
× V
LBO
) represents an approximated input
power (I
L
× V
ac
). It is illustrated in Figure 48.
Current
mirror
OPL
V
in
R
SENSE
R
CS
CS
LBO
R
LBOU
R
LBOL
C
LBO
I
CS
Figure 48. PFC Over-Power Limitation Configuration
I
L
> 275 mVA?
When the product (I
CS
× V
LBO
) is greater than
a permissible level 275 mVA, the device turns off the PFC
driver so that the input power is limited. The OPL is
automatically deactivated when the product (I
CS
× V
LBO
) is
lower than the 275 mVA level. This 275 mVA level
corresponds to the approximated input power (I
L
× Vac) to
be smaller than the particular expression in Equation 15.
I
CS
V
LBO
t 275 mVA
(eq. 15
)
ǒ
I
L
R
SENSE
R
CS
Ǔ
ǒ
22
Ǹ
K
LBO
p
@ V
ac
Ǔ
t 275 mVA
I
L
@ V
ac
t
R
CS
@ p
R
SENSE
@ K
LBO
@ 97 mVA
Where
K
LBO
+
R
LBOL
R
LBOU
) R
LBOL
PFC Reference Section
The internal reference voltage (V
PREF
) is trimmed to be
±2% accurate over the temperature range (the typical value
is 2.5 V). V
PREF
is the reference used for the regulation of
PFC section.
PFC Feedback and Compensation
OTA
V
bulk
V
in
R
FBU
R
FBL
R
Z
C
Z
C
P
V
CTRL(min)
To Multiplier of V
M
pin
FB
V
CTRL
V
PREF
Figure 49. V
CTRL
Type-2 Compensation
The output voltage V
bulk
of the PFC circuits is sensed at
FB pin via the resistor divider (R
FBL
and R
FBU
) as shown in
Figure 49. V
bulk
is regulated as described in Equation 16.
V
bulk
+ V
PREF
R
FBU
) R
FBL
R
FBL
(eq. 16)
The feedback signal V
FB
represents the output voltage
V
bulk
and will be used in the output voltage regulation,
Over-Voltage Protection (OVP), fast transient response, and
Under-Voltage Protection (UVP)
The Operational Trans-conductance Amplifier (OTA)
constructs a control voltage, V
CTRL
, depending on the
output power and hence V
bulk
. The operating range of
V
CTRL
is from V
CTRL(min)
to V
CTRL(max)
. The signal used
for PFC duty modulation is after decreasing a offset voltage,
V
CTRL(min)
, i.e. V
CTRL
−V
CTRL(min)
.
This control voltage V
CTRL
is a roughly constant voltage
that comes from the PFC output voltage V
bulk
that is a slowly
varying signal. The bandwidth of V
CTRL
can be additionally
limited by inserting the external type-2 compensation
components (that are R
Z
, C
Z
, and C
P
as shown in Figure 49).
It is recommended to limit cross over frequency of open loop
system below 20 Hz typically if the input ac voltage is 50 Hz
to achieve power factor correction purpose.
The transformer of V
bulk
to V
CTRL
is as described in
Equation 16 if C
Z
>> C
P
. G
EA
is the error amplifier gain.
V
CTRL
V
bulk
+
R
FBL
@ G
EA
R
Z
R
FBL
) R
FBU
@
1 ) sR
Z
C
Z
sR
Z
C
Z
ǒ
1 ) sR
Z
C
P
Ǔ
(eq. 17)

NCP1910GEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
BOARD DEMO NCP1910DEMO-B-TLS
Lifecycle:
New from this manufacturer.
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