NCP1910
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34
If V
bulk
reaches the LLC stop level (BO level adjusted
by BO
adj
pin), the LLC stops; or if V
bulk
drops slowly,
e.g. light load, LLC drivers (ML and MU pins) will
stop 5 ms after PG
out
pin is released (t
DEL2
).
As shutdown by line brown-out situation, PFCok signal will
be pulled down:
PG
out
pin is released open once this internal PFCok
signal is low.
LLC drivers (ML and MU pins) will stop 5 ms after
PG
out
pin is released open (t
DEL2
).
V
bulk
time
95%
LLC works
off
off
t
DEL1
t
DEL2
5 ms
PG level
20 ms
PG
out
BO level
Figure 61. The Timing for t
DEL1
and t
DEL2
Remote On/Off (On/Off Pin)
NCP1910 reserves one dedicated pin for remote control
feature at on/off pin:
When the on/off pin is pulled below 1 V, the PFC starts
operation. 20 ms after V
bulk
is above 95% of target
level, LLC starts.
When the on/off pin is above 3 V, the device stops both
PFC and LLC immediately and keeps low
consumption. Figure 62 depicts the relationship
between the operation mode and on/off pin.
On/off pin
State
ON
V
on
V
off
On/off pin
I
CC
TBD
< 600 mA
OFF
Figure 62. Remote on/off (on/off Pin)
V
CC
Under-Voltage LockOut (UVLO)
The device incorporates an Under-Voltage Lockout block
to prevent the circuit from operating when V
CC
is too low in
order to ensure a proper operation. An UVLO comparator
monitors V
CC
pin voltage to allow the NCP1910 to operate
when V
CC
exceeds V
CC(on)
. The comparator incorporates
some hysteresis (V
CC(Hys)
) to prevent erratic operation as
the V
CC
crosses the threshold. When V
CC
goes below the
UVLO comparator lower threshold (V
CC(min)
), the circuit
turns off. It is illustrated in Figure 63. After startup, the
operating range is between 9 V and 20 V.
NCP1910
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35
V
CC
State
ON
V
CC(min)
V
CC(on)
I
CC
TBD
< 100mA
OFF
Figure 63. V
CC
Under-Voltage LockOut (UVLO)
V
CC
Bias the Controller
It is recommended to add a typical 1 nF to 100 nF
decoupling capacitor next to the V
CC
pin for proper
operation. The hysteresis between V
CC(on)
and V
CC(min)
is
small because the NCP1910 is supposed to be biased by
external power source. Therefore it is recommended to
make a low-voltage source to bias NCP1910, e.g. the
standby power supply.
Thermal Shutdown
An internal thermal circuitry disables the circuit gate drive
and then keeps the power switch off when the junction
temperature exceeds TSD level. The output stage is then
enabled once the temperature drops below typically 110°C
(i.e. TSD − TSD
hyste
). The thermal shutdown is provided to
prevent possible device failures that could result from an
accidental over-heating.
5 V Reference
The V
REF
pin provides an accurate (±2% typically) 5 V
reference voltage. The Power-Good and Brown-Out of LLC
converter, and the frequency foldback level (fold pin) of
PFC can hence can get an accurate reference voltage by
resistor dividers.
Latched Protections and Reset
As depicated in the above sections, there are 3 fault modes
that latch off both PFC and LLC:
PFC abnormal
PFC OVP2
LLC CS/FF pin is above V
CS2
To release from the latch-off mode, NCP1910 offers 3
ways:
Recycle V
CC
so that V
CC
is below V
CC(min)
and back
to above V
CC(on)
again.
Recycle the remote on/off function, which toggles
on/off pin high and low again.
Recycle the line brown-out function, which could be
done by unplug and re-plug the ac input.
ORDERING INFORMATION
Device Version Marking Package Shipping
NCP1910A65DWR2G 65 kHz − A NCP1910A65 SOIC−24 WB Less Pin 21
(Pb-Free)
1000 / Tape & Reel
NCP1910B65DWR2G 65 kHz − B NCP1910B65 SOIC−24 WB Less Pin 21
(Pb-Free)
1000 / Tape & Reel
NCP1910A100DWR2G 100 kHz − A NCP1910A10 SOIC−24 WB Less Pin 21
(Pb-Free)
1000 / Tape & Reel
NCP1910B100DWR2G 100 kHz − B NCP1910B10 SOIC−24 WB Less Pin 21
(Pb-Free)
1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1910
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36
PACKAGE DIMENSIONS
SOIC−24 WB LESS PIN 21
CASE 752AB
ISSUE O
b
E
M
0.25 C
SEATING
PLANE
A1
e
M
L
DETAIL A
END VIEW
h
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.10 mm TOTAL IN EXCESS OF ’b’ AT MAXIM-
UM MATERIAL CONDITION.
4. DIMENSIONS b AND c APPLY TO THE FLAT SEC-
TION OF THE LEAD AND ARE MEASURED
BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
5. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
6. DIMENSIONS D AND E1 ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH,
PROTRUSIONS, TIE BAR BURRS, OR GATE
BURRS BUT INCLUSIVE OF ANY MOLD
MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
7. DIMENSIONS A AND B ARE TO BE DETERMINED
AT DATUM H.
8. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
9. THIS CHAMFER IS OPTIONAL. IF IT IS NOT
PRESENT, THEN A PIN 1 IDENTIFIER MUST BE
LOCATED IN THE INDICATED AREA.
L2
NOTES 3 & 4
PIN 1
12
1
24 13
TOP VIEW
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
b 0.31 0.51
e 1.27 BSC
h 0.25 0.75
J 0.20 0.33
A1 0.10 0.29
L 0.40 1.27
M 0 8
__
D
E1
SIDE VIEW
11.00
23X
0.52
23X
1.62
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
D 15.40 BSC
E 10.30 BSC
E1 7.50 BSC
L2 0.25 BSC
RECOMMENDED
D
INDICATOR
A-B D
NOTE 7
0.10 C D
0.33 C
0.20 C A-B
NOTES 5 & 6
24X
2X
2X
B
A
NOTE 7
2X
0.10 C
C
A
NOTE 8
0.10 C
x 45
c
NOTE 9
DETAIL A
C
H

NCP1910GEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
BOARD DEMO NCP1910DEMO-B-TLS
Lifecycle:
New from this manufacturer.
Delivery:
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